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a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D revision: v1.00 date: ???? ??? ? 01 ? ???? ??? ? 01 ?
rev. 1.00 ? ???? ??? ? 01 ? rev. 1.00 3 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D table of contents eates cpu feat ? res ......................................................................................................................... ? periphera ? feat ? res ................................................................................................................. ? genera? description ......................................................................................... 7 se?ection tab?e ................................................................................................. 7 pin assignment ........... ..................................................................................... 9 pin descriptions ............................................................................................ 10 ht ?? f ? 4d ............................................................................................................................. 10 ht ?? f ? 5d .............................................................................................................................. 11 abso??te maxim?m ratings .......................................................................... 1? d.c. characteristics ....................................................................................... 1? a.c. characteristics ....................................................................................... 14 lvd and lvr e?ectrica? characteristics ........... ............................................ 15 a/d converter characteristics ........... ........................................................... 1? power-on reset characteristics ........... ........................................................ 17 s?stem architect?re ...................................................................................... 18 c ? ocking and pipe ? ining ......................................................................................................... 18 program co ? nter ................................................................................................................... 19 stack ..................................................................................................................................... ? 0 arithmetic and logic unit C alu ........................................................................................... ? 0 f?ash program memor? ................................................................................. ?1 str ? ct ? re ................................................................................................................................ ? 1 specia ? vectors ..................................................................................................................... ? 1 look- ? p tab ? e ............. ........................................................................................................... ?? tab ? e program examp ? e ........................................................................................................ ?? in circ ? it programming ......................................................................................................... ? 4 ram data memor? ......................................................................................... ?5 str ? ct ? re ................................................................................................................................ ? 5 specia? f?nction register description ........................................................ ?8 indirect addressing registers C iar0 ? iar1 ......................................................................... ? 8 memor ? pointers C mp0 ? mp1 .............................................................................................. ? 8 bank pointer C bp ................................................................................................................. ? 9 acc ? m ?? ator C acc ............................................................................................................... ? 9 program co ? nter low register C pcl .................................................................................. ? 9 look- ? p tab ? e registers C tblp ? tbhp ? tblh ..................................................................... 30 stat ? s register C status .................................................................................................... 30
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ? ???? ??? ?01? rev. 1.00 3 ???? ??? ? 01 ? eeprom data memory ........... ....................................................................... 32 eeprom data memor ? str ? ct ? re ........................................................................................ 3 ? eeprom registers ............ .................................................................................................. 3 ? reading data from the eeprom ......................................................................................... 34 writing data to the eeprom ................................................................................................ 34 write protection ..................................................................................................................... 34 eeprom interr ? pt ............. ................................................................................................... 34 programming considerations ............. ................................................................................... 35 oscillator ........................................................................................................ 36 osci ?? ator overview ............. .................................................................................................. 3 ? system clock confgurations ................................................................................................ 3 ? externa ? cr ? sta ? /ceramic osci ?? ator C hxt ........................................................................... 37 interna ? high speed rc osci ?? ator C hirc ........................................................................... 38 interna ? 3 ? khz osci ?? ator C lirc ........................................................................................... 38 externa ? 3 ? .7 ? 8khz cr ? sta ? osci ?? ator C lxt ............. ........................................................... 38 s ? pp ? ementar ? osci ?? ator ...................................................................................................... 39 operating modes and system clocks ......................................................... 40 s ? stem c ? ocks ...................................................................................................................... 40 s ? stem operation modes ...................................................................................................... 41 contro ? register .................................................................................................................... 4 ? fast wake- ? p ........................................................................................................................ 44 operating mode switching .................................................................................................... 45 standb ? c ? rrent considerations ........................................................................................... 49 wake- ? p ................................................................................................................................ 49 programming considerations ............. ................................................................................... 49 watchdog timer ........... .................................................................................. 50 watchdog timer c ? ock so ? rce .............................................................................................. 50 watchdog timer contro ? register ............. ............................................................................ 50 watchdog timer operation ................................................................................................... 51 reset and initialisation .................................................................................. 52 reset f ? nctions ............. ....................................................................................................... 53 reset initia ? conditions ......................................................................................................... 55 input/output ports ......................................................................................... 60 i/o resistor lists ................................................................................................................... ? 0 p ??? -high resistors ................................................................................................................ ? 1 port a wake- ? p ............. ........................................................................................................ ?? pin-remapping f ? nctions ...................................................................................................... ? 4
rev. 1.00 4 ???? ??? ? 01 ? rev. 1.00 5 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D timer modules C tm .......... ............................................................................ 66 introd ? ction ........................................................................................................................... ?? tm operation ............. ........................................................................................................... ? 7 tm c ? ock so ? rce ............. ...................................................................................................... ? 7 tm interr ? pts ......................................................................................................................... ? 7 tm externa ? pins ................................................................................................................... ? 8 tm inp ? t/o ? tp ? t pin contro ? registers ............. .................................................................... ? 8 programming considerations ............. ................................................................................... 73 compact type tm C ctm .............................................................................. 74 compact tm operation ......................................................................................................... 74 compact t ? pe tm register description ................................................................................ 75 compact t ? pe tm operation modes .................................................................................... 79 standard type tm C stm .......... .................................................................... 85 standard tm operation ............. ............................................................................................ 85 standard t ? pe tm register description ............................................................................... 8 ? standard t ? pe tm operation modes .................................................................................... 90 capt ? re inp ? t mode .............................................................................................................. 98 enhanced type tm C etm ........... ................................................................ 100 enhanced tm operation ..................................................................................................... 100 enhanced t ? pe tm register description ............................................................................ 101 enhanced t ? pe tm operation modes ................................................................................. 108 analog to digital converter .......... .............................................................. 124 a/d overview ............. ......................................................................................................... 1 ? 4 a/d converter register description .................................................................................... 1 ? 4 a/d operation ..................................................................................................................... 1 ? 8 a/d inp ? t pins ............. ........................................................................................................ 1 ? 9 s ? mmar ? of a/d conversion steps ............. ........................................................................ 130 programming considerations ............. ................................................................................. 131 a/d transfer f ? nction ............. ............................................................................................ 131 a/d programming examp ? es ............................................................................................... 13 ? interrupts ...................................................................................................... 134 interr ? pt registers ............................................................................................................... 134 interr ? pt operation .............................................................................................................. 140 externa ? interr ? pt ............. .................................................................................................... 14 ? m ?? ti-f ? nction interr ? pt ........................................................................................................ 14 ? a/d converter interr ? pt ....................................................................................................... 14 ? time base interr ? pt ............................................................................................................. 143 lvd interr ? pt ....................................................................................................................... 144 tm interr ? pt ............. ............................................................................................................ 144 interr ? pt wake- ? p f ? nction ................................................................................................. 144 programming considerations ............. ................................................................................. 145
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 4 ???? ??? ?01? rev. 1.00 5 ???? ??? ? 01 ? low voltage detector C lvd .......... ............................................................. 146 lvd register ............. .......................................................................................................... 14 ? lvd operation ..................................................................................................................... 147 confguration options ................................................................................. 148 application circuits ........... .......................................................................... 149 instruction set .............................................................................................. 150 introd ? ction ......................................................................................................................... 150 instr ? ction timing ................................................................................................................ 150 moving and transferring data ............................................................................................. 150 arithmetic operations .......................................................................................................... 150 logica ? and rotate operations ............. ............................................................................... 151 branches and contro ? transfer ........................................................................................... 151 bit operations ..................................................................................................................... 151 tab ? e read operations ....................................................................................................... 151 other operations ............. .................................................................................................... 151 instruction set summary .......... .................................................................. 152 tab ? e conventions ............................................................................................................... 15 ? package information ................................................................................... 163 1 ? -pin dip (300mi ? ) o ? t ? ine dimensions ............. ................................................................ 1 ? 3 1 ? -pin nsop (150mi ? ) o ? t ? ine dimensions ......................................................................... 1 ? 5 ? 0-pin dip (300mi ? ) o ? t ? ine dimensions ............. ................................................................ 1 ?? ? 0-pin sop (300mi ? ) o ? t ? ine dimensions ........................................................................... 1 ? 8 ? 4-pin skdip (300mi ? ) o ? t ? ine dimensions ............. ........................................................... 1 ? 9 ? 4-pin sop (300mi ? ) o ? t ? ine dimensions ........................................................................... 171 ? 8-pin skdip (300mi ? ) o ? t ? ine dimensions ............. ........................................................... 17 ? ? 8-pin sop (300mi ? ) o ? t ? ine dimensions ........................................................................... 173 ree ? dimensions ................................................................................................................. 174 carrier tape dimensions ..................................................................................................... 175
rev. 1.00 6 july 26, 2012 rev. 1.00 7 july 26, 2012 a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D features cpu features ? operating voltage: ? f sys = 8mhz: 2.2v~5.5v ? f sys = 12mhz: 2.7v~5.5v ? f sys = 20mhz: 4.5v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd = 5v ? power down and wake-up functions to reduce power consumption ? four oscillator types: external high frequency crystal C hxt internal rc C hirc external 32.768khz crystal C lxt internal 32khz rc C lirc ? multi-mode operation: normal, slow, idle and sleep ? fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? up to 8-level subroutine nesting ? bit manipulation instruction peripheral features ? program memory: 2k x16 ~ 4k x 16 ? data memory: 96 x 8 ~ 192 x 8 ? eeprom memory: 64 x 8 ? watchdog t imer function ? up to 26 bidirectional i/o lines ? multiple pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output or single pulse output function ? dual t ime-base functions for generation of fxed time interrupt signal ? up to 8 channels 12-bit adc ? low voltage reset function ? low voltage detect function ? led driver ? wide range of available package types
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ? ???? ??? ?01? rev. 1.00 7 ???? ??? ? 01 ? general description the series of devices are flash memory a/d type 8-bit high performance risc architecture microcontrollers. of fering users the convenience of flash memory multi-programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory for application program data storage. analog feature includes a multi-channel 12-bit a/d converter. multiple and extremely fexible t imer modules provide timing, pulse generation and pwm generation functions. protective features such as an internal w atchdog t imer, low v oltage reset and low v oltage detector coupled with excellent noise imm unity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a f ull c hoice o f hxt , hi rc, l xt a nd l irc o scillator f unctions a re p rovided i ncluding a f ully integrated system oscillator which requires no external components for its implementation. the ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, t ime-base functions along with many other features e nsure t hat t he de vices wi ll fnd e xcellent use i n a pplications suc h a s e lectronic m etering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. selection table most features are common to all devices, the main feature distinguishing them are memory capacity, i/o count, tm features, stack capacity and package types. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o external interrupt ht ?? f ? 4d ? . ? v~5.5v ? k x 1 ? 9 ? x 8 ? 4 x 8 ?? ? ht ?? f ? 5d ? . ? v~5.5v 4k x 1 ? 19 ? x 8 ? 4 x 8 ?? ? part no. a/d converter timer module led driver stacks package ht ?? f ? 4d 1 ? -bit x 8 10-bit ctm x 1 10-bit stm x 1 8 x ? 8 1 ? dip/nsop ? 0dip/sop ? 4skdip/sop ht ?? f ? 5d 1 ? -bit x 8 10-bit ctm x 1 10-bit etm x 1 8 x 8 8 ? 0dip/sop ? 4/ ? 8skdip/sop note: as devices exist in more than one package format, the table refects the situation for the package with the most pins.
rev. 1.00 8 ???? ??? ? 01 ? rev. 1.00 9 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D block diagram watchdog timer 8-bit risc mcu core reset circuit interrupt controller erc/hxt oscillator 12-bit a/d converter lirc oscillator hirc oscillator ram data stack memory low voltage reset low voltage detect tm1 tm0 flash/eeprom programming circuitry (icp) flash program memory tb0/tb1 eeprom data memory i/o
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 8 ???? ??? ?01? rev. 1.00 9 ???? ??? ? 01 ? pin assignment

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rev. 1.00 10 ???? ??? ? 01 ? rev. 1.00 11 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D pin descriptions with the exception of the power pins, all pins on these devices can be referenced by their port name, e.g. p a.0, p a.1 etc, which refer to the digital i/o function of the pins. however some of these port pins are also shared with other function such as the analog to digital converter , t imer module pins etc. the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. ht66f24d function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb5 port b pbpu st cmos pc0~pc7 port c pcpu st cmos an0~an7 a/d converter inp ? t acerl an pa0~pa ?? pb3~pb5 ? pb1~pb ? vref a/d converter reference inp ? t adcr1 an pa ? tck0 tm0 inp ? t prm0 st pa ?? pc ? tck1 tm1 inp ? t prm0 st pb0 ? pc3 tp0_0 ? tp0_1 ? tp0_ ? tm0 i/o tmpc0 st cmos pa3 ? pa0 ? pa7 tp1_0 ? tp1_1 ? tp1_ ? tm1 i/o tmpc0 st cmos pa4 ? pa1 ? pb1 int0 externa ? interr ? pt 0 prm0 st pa ?? pc0 int1 externa ? interr ? pt 1 prm0 st pb0 ? pc1 osc1 hxt pin co hxt pa ? osc ? hxt pin co hxt pa5 xt1 lxt pin co lxt pa4 xt ? lxt pin co lxt pa3 vdd power s ? pp ?? * pwr vss gro ? nd* pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt t rigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: a vdd is the adc power supply and is bonded together internally with vdd while a vss is the adc ground pin and is bonded together internally with vss.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 10 ???? ??? ?01? rev. 1.00 11 ???? ??? ? 01 ? HT66F25D pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc7 port c pcpu st cmos pd0~pd1 port d pdpu st cmos an0~an7 a/d converter inp ? t acerl an pa0~pa ?? pb3~pb7 vref a/d converter reference inp ? t adcr1 an pa ? tck0 tm0 inp ? t prm0 st pa ?? pc ? tck1 tm1 inp ? t prm0 st pb0 ? pc3 tp0_0 ? tp0_1 ? tp0_ ? tm0 i/o tmpc0 st cmos pa3 ? pa0 ? pa7 tp1a_0 ? tp1a_1 tm1 i/o tmpc0 st cmos pa5 ? pb ? tp1b_0 ? tp1b_1 ? tp1b_ ? tm1 i/o tmpc0 st cmos pa4 ? pa1 ? pb1 int0 externa ? interr ? pt 0 prm0 st pa ?? pc0 int1 externa ? interr ? pt 1 prm0 st pb0 ? pc1 osc1 hxt pin co hxt pa ? osc ? hxt pin co hxt pa5 xt1 lxt pin co lxt pa4 xt ? lxt pin co lxt pa3 vdd power s ? pp ?? * pwr vss gro ? nd* pwr note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt t rigger input cmos: cmos output; nmos: nmos output scom: software controlled lcd com; an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: a vdd is the adc power supply and is bonded together internally with vdd while a vss is the adc ground pin and is bonded together internally with vss.
rev. 1.00 1 ? ???? ??? ? 01 ? rev. 1.00 13 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D absolute maximum ratings supply v oltage .............. .................................................................................. v ss -0.3v to v ss +6.0v input v oltage .............. .................................................................................... v ss -0.3v to v dd +0.3v i ol total .................................................................................................. 100ma total power dissipation .............. .......................................................................................... 500mw storage t emperature ............... ................................................................................... -50 c to 125c operating t emperature .............. .................................................................................. -40 c to 85 c i oh t otal .......... ...................................................................................... -100ma note: t hese a re st ress ra tings on ly. st resses e xceeding t he ra nge spe cified un der absolute maximum ratings may caus e substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating vo ? tage (htx/hirc osc) f sys =8mhz ? . ? 5.5 v f sys =1 ? mhz ? .7 5.5 v f sys = ? 0mhz 4.5 5.5 v i dd1 operating c ? rrent ? norma ? mode ? f sys =f h ? f s =f sub =f lxt or f lirc (hxt ? hirc) 3v no ? oad ? f h =4mhz ? adc off ? wdt enab ? e 0.7 1.1 ma 5v 1.8 ? .7 ma 3v no ? oad ? f h =8mhz ? adc off ? wdt enab ? e 1. ? ? .4 ma 5v 3.3 5.0 ma 3v no ? oad ? f h =1 ? mhz ? adc off ? wdt enab ? e ? . ? 3.3 ma 5v 5.0 7.5 ma i dd ? operating c ? rrent ? norma ? mode ? f sys =f h ? f s =f sub =f lxt or f lirc (hxt) 5v no ? oad ? f h = ? 0mhz ? adc off ? wdt enab ? e ? .0 9.0 ma i dd3 operating c ? rrent ? s ? ow mode ? f sys =f l (lxt ? lirc) 3v no ? oad ? f sys =lxt ? adc off ? wdt enab ? e ? lxtlp=0 15 30 5v 30 50 3v no ? oad ? f sys =lxt ? adc off ? wdt enab ? e ? lxtlp=1 10 ? 5 5v ? 5 45 3v no ? oad ? f sys =lirc ? adc off ? wdt enab ? e 10 ? 0 5v ? 0 40 i idle1 idle0 mode stanb ? c ? rrent (lxt or lirc on) 3v no ? oad ? adc off ? wdt enab ? e 1.5 3.0 5v 3.0 ? .0 i idle ? idle1 mode stanb ? c ? rrent (hxt ? hirc) 3v no ? oad ? adc off ? wdt enab ? e ? f sys =1 ? mhz on 0.55 0.83 ma 5v 1.30 ? .00 ma i sleep1 sleep0 mode stanb ? c ? rrent (lxt and lirc off) 3v no ? oad ? adc off ? wdt disab ? e 1.0 5v ? .0 i sleep ? sleep1 mode stanb ? c ? rrent (lxt or lirc on) 3v no ? oad ? adc off ? wdt enab ? e 1.5 3.0 5v ? .5 5.0
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1? ???? ??? ?01? rev. 1.00 13 ???? ??? ? 01 ? symbol parameter test conditions min. typ. max. unit v dd conditions v il1 inp ? t low vo ? tage for i/o ports or inp ? t pins 0 0.3v dd v v ih1 inp ? t high vo ? tage for i/o ports or inp ? t pins 0.7v dd v dd v i ol1 i/o port sink c ? rrent (pa0~pa ?? pb0 ? d0~pd1) 3v v ol = 0.1v dd 4 8 ma 5v v ol = 0.1v dd 10 ? 0 ma i oh1 i/o port ? so ? rce c ? rrent (pa0~pa ?? pb0 ? d0~pd1) 3v v oh = 0.9v dd - ? -4 ma 5v v oh = 0.9v dd -5 -10 ma i ol ? i/o port sink c ? rrent (pa7 ? pb1~pb7) 3v v ol = 0.1v dd 1 ? 3 ? ma 5v v ol = 0.1v dd 40 80 ma i oh ? i/o port ? so ? rce c ? rrent (pa7 ? pb1~pb7) 3v v oh = 0.9v dd - ? -4 ma 5v v oh = 0.9v dd -5 -10 ma i ol3 i/o port sink c ? rrent (pc0~pc7) 3v v ol = 0.1v dd 4 8 ma 5v v ol = 0.1v dd 10 ? 0 ma i oh3 i/o port ? so ? rce c ? rrent (pc0~pc7) 3v v oh = 0.9v dd -4 -8 ma 5v v oh = 0.9v dd -10 - ? 0 ma r ph p ??? -high resistance of i/o ports 3v ? 0 ? 0 100 k 5v 10 30 50 k
rev. 1.00 14 ???? ??? ? 01 ? rev. 1.00 15 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D a.c. characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd condition f cpu operating c ? ock ? . ? ~5.5v dc 8 mhz ? .7~5.5v dc 1 ? mhz 4.5~5.5v dc ? 0 mhz f sys s ? stem c ? ock (hxt) ? . ? ~5.5v 0.4 8 mhz ? .7~5.5v 0.4 1 ? mhz 4.5~5.5v 0.4 ? 0 mhz f hirc s ? stem c ? ock (hirc) 3v/5v ta= ? 5c - ? % 4 + ? % mhz 3v/5v ta= ? 5c - ? % 8 + ? % mhz 5v ta= ? 5c - ? % 1 ? + ? % mhz 3v/5v ta=0c~70c -5% 4 +5% mhz 3v/5v ta=0c~70c -4% 8 +4% mhz 5v ta=0c~70c -5% 1 ? +3% mhz ? . ? v~3. ? v ta=0c~70c -7% 4 +7% mhz 3.0v~5.5v ta=0c~70c -5% 4 +9% mhz ? . ? v~3. ? v ta=0c~70c - ? % 8 +4% mhz 3.0v~5.5v ta=0c~70c -4% 8 +9% mhz 3.0v~5.5v ta=0c~70c - ? % 1 ? +7% mhz ? . ? v~3. ? v ta=-40c~85c -1 ? % 4 +8% mhz 3.0v~5.5v ta=-40c~85c -10% 4 +9% mhz ? . ? v~3. ? v ta=-40c~85c -15% 8 +4% mhz 3.0v~5.5v ta=-40c~85c -8% 8 +9% mhz 3.0v~5.5v ta=-40c~85c -1 ? % 1 ? +7% mhz f lxt s ? stem c ? ock (lxt) 3 ? 7 ? 8 hz f lirc s ? stem c ? ock (lirc) 5v ta = ? 5c -10% 3 ? +10% khz ? . ? v~5.5v ta = -40c to 85c -30% 3 ? + ? 0% khz t timer tckn inp ? t pin p ?? se width 0.3 s t int interr ? pt p ?? se width 10 s t sst s ? stem start- ? p timer period (wake- ? p from halt ? f sys off at halt state) f sys = hxt 1 ? 8 t sys f sys = hirc 1 ? t sys f sys = lirc ? t sys s ? stem start- ? p timer period (wake- ? p from halt ? f sys on at halt state) ? t sys t rstd s ? stem reset de ? a ? time (power on reset) ? 5 50 100 ms s ? stem reset de ? a ? time (an ? reset except power on reset) 8.3 1 ? .7 33.3 ms t eerd eeprom read time f sys = ? 0mhz 4 t sys t eewr eeprom write time 1 ? 4 ms 1rwh w sys i sys dd dud i ud du iu d s dsdu d d d d y d s
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 14 ???? ??? ?01? rev. 1.00 15 ???? ??? ? 01 ? lvd and lvr electrical characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low vo ? tage reset vo ? tage lvr enab ? e ? v lvr = ? .1v -5% t ? p. ? .1 +5% t ? p. v v lvr ? lvr enab ? e ? v lvr = ? .55v ? .55 v v lvr3 lvr enab ? e ? v lvr = 3.15v 3.15 v v lvr4 lvr enab ? e ? v lvr = 3.8v 3.8 v v lvd1 low vo ? tage detector vo ? tage lvden = 1 ? v lvd = ? .0v -5% t ? p. ? .0 +5% t ? p. v v lvd ? lvden = 1 ? v lvd = ? . ? v ? . ? v v lvd3 lvden = 1 ? v lvd = ? .4v ? .4 v v lvd4 lvden = 1 ? v lvd = ? .7v ? .7 v v lvd5 lvden = 1 ? v lvd = 3.0v 3.0 v v lvd ? lvden = 1 ? v lvd = 3.3v 3.3 v v lvd7 lvden = 1 ? v lvd = 3. ? v 3. ? v v lvd8 lvden = 1 ? v lvd = 4.0v 4.0 v i lvr additiona ? power cons ? mption 3v 30 45 a 5v ? 0 90 a i lvd additiona ? power cons ? mption if lvd is used 3v lvd disab ? e lvd enab ? e (lvr enab ? e) 30 45 a 5v ? 0 90 a t lvr low vo ? tage width to reset 1 ? 0 ? 40 480 s t lvd low vo ? tage width to interr ? pt ? 0 45 90 s t lvds lvdo stab ? e time for lvr enab ? e ? lvd off on 15 s for lvr disab ? e ? lvd off on 15 s t sreset software reset width to reset 45 90 1 ? 0 s 0.1
rev. 1.00 1 ? ???? ??? ? 01 ? rev. 1.00 17 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D a/d converter characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating vo ? tage ? .7 5.5 v v adi a/d converter inp ? t vo ? tage 0 v ref v v ref a/d converter reference vo ? tage ? av dd v v bg reference vo ? tage with b ? ffer vo ? tage -3% 1. ? 5 +3% v dnl1 differentia ? non- ? inearit ? ? .7v v ref =av dd =v dd ? t adck =0.5 s ? ta= ? 5 c -3 +3 lsb 3v 5v dnl ? differentia ? non- ? inearit ? ? .7v v ref =av dd =v dd ? t adck =0.5s, ta=-40c~85c -4 +4 lsb 3v 5v inl1 integra ? non- ? inearit ? ? .7v v ref =av dd =v dd ? t adc =0.5 s ? ta= ? 5 c -4 +4 lsb 3v 5v inl ? integra ? non- ? inearit ? ? .7v v ref =av dd =v dd t adck =0.5s, ta=-40c~85c -8 +8 lsb 3v 5v i adc additiona ? power cons ? mption if a/d converter is used 3v no ? oad ? t adck =0.5s 0.9 1.35 ma 5v no ? oad ? t adck =0.5s 1. ? 1.8 ma t adck a/d converter c ? ock period 0.5 10 s t adc a/d conversion time (inc ?? de samp ? e and ho ? d time) 1 ? bit a/d converter 1 ? t adck t ads a/d converter samp ? ing time 4 t adck t on ? st a/d converter on-to-start time ? s t bgs v bg t ? rn on stab ? e time ? 00 s
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1? ???? ??? ?01? rev. 1.00 17 ???? ??? ? 01 ? power-on reset characteristics ta= ? 5c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start vo ? tage to ens ? re power-on reset 100 mv rr vdd v dd raising rate to ens ? re power-on reset 0.035 v/ms t por minim ? m time for v dd sta ? s at v por to ens ? re power-on reset 1 ms
rev. 1.00 18 ???? ??? ? 01 ? rev. 1.00 19 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addresse d. the simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility . this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt , hirc, lxt or lirc oscillator is subdivided into four internall y generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. the exce ption to this are instructions where the content s of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? ? ? ? system clocking and pipelining
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 18 ???? ??? ?01? rev. 1.00 19 ???? ??? ? 01 ?
? ? ? ? ? ? ? ? ? ? instruction fetching for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "jmp" or "cal l" t hat de mand a j ump t o a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses such as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter high byte low byte (pcl register) ht ?? f ? 4d pc10~pc8 pcl7~pcl0 ht ?? f ? 5d pc11~pc8 pcl7~pcl0 program counter the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into this register , a short program jump can be executed directly , however , as only this low byte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch.
rev. 1.00 ? 0 ???? ??? ? 01 ? rev. 1.00 ?1 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D stack this is a special part of the memory which is used to save the contents of the program counter only . the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be execu ted which will result in a stack overfow . precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost.
device stack levels ht ?? f ? 4d 8 ht ?? f ? 5d 8 arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the that carries out arithmetic and logic operations of the instruction set. connected to the main data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, , orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?0 ???? ??? ?01? rev. 1.00 ? 1 ???? ??? ? 01 ? flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. by using the appropriate programming tools, these flash device s of fer users the fexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the program memory has a capacity of 2kx16 bits to 4kx16 bits. the program memory is addressed by the program counter and also contains data, tabl e informati on and interrupt entries. table data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. device capacity ht ?? f ? 4d ? k x 1 ? ht ?? f ? 5d 4k x 1 ?

program memory structure special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.00 ?? ???? ??? ? 01 ? rev. 1.00 ?3 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the "t abrd[m]" or "t abrdl[m]" instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as "0". the accompanying diagram illustrates the addressing data fow of the look-up table.

table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k program memory of the ht66f24d device. the table pointer is setup here to have an initial value of "06h". this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrd [m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "t abrd [m]" instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?? ???? ??? ?01? rev. 1.00 ? 3 ???? ??? ? 01 ? table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a ,06h ; initialise low table pointer - note that this address mov t blp,a ; is referenced mov a ,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at ; program memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at ; program memory address 705h transferred to tempreg2 and tblh ; in this example the data 1ah is transferred to tempreg1 and ; data 0fh to register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.00 ? 4 ???? ??? ? 01 ? rev. 1.00 ?5 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. holtek writer pins mcu programming pins pin description icpda pa0 programming seria ? data icpck pa ? programming c ? ock icpms pb0 programming mode se ? ect vdd vdd power s ? pp ?? vss vss gro ? nd the program memory can be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. t wo additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the icpms pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the p a0 and p a2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * m ay be r esistor o r c apacitor. t he r esistance of * m ust be g reater than 1 k o r t he c apacitance o f * must b e l ess t han 1 nf.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?4 ???? ??? ?01? rev. 1.00 ? 5 ???? ??? ? 01 ? ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locatio ns within this area are read and write accessible under program control. the special purpose data memory registers are accessible in all banks. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for all devices is the address 00h. 00 h 3 fh 40 h 9 fh specia? p?rpose data memor? genera? p?rpose data memor? bank 0 eec bank 0 & bank 1 ht 66f 24 d ram data memory structure bank 1 00 h 3 fh 40 h ffh specia? p?rpose data memor? genera? p?rpose data memor? bank 0 eec bank 0 & bank 1 ht 66 f 25 d ram data memory structure bank 1 ram data memory structure device capacity address ht ?? f ? 4d 9 ? x 8 40h ~ 9fh ht ?? f ? 5d 19 ? x 8 40h ~ ffh general purpose data memory structure
rev. 1.00 ?? ???? ??? ? 01 ? rev. 1.00 ?7 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D 00h iar 0 01h mp 0 0?h iar 1 03h mp 1 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh smod 0 ch lvdc 0 dh integ 0 eh wdtc 0 fh tbc 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh ?0h ?1h pa pac pbpu pb pbc 1 eh pcpu pc pcc ?9 h adrh ?8 h adrl ? bh ? ah ? ch adcr 0 adcr 1 acerl ? dh 35 h tm 1c1 34 h tm 1c0 un?sed 3? h 38 h tm 1 dh 37 h tm 1 dl 3 ah tm 1 ah 39 h tm 1 al un?sed 3 bh 3 dh 3 eh 3 fh bp 13h 14h mfi 0 15h mfi 1 1?h 17h ?5 h ?? h ?7 h prm 0 tmpc 0 ? fh tm 0c1 ? eh tm 0c0 30 h 3? h tm 0 dh 31 h tm 0 dl tm 0 ah 33 h tm 0 al : un?sed ? read as 00 h bank 0 bank 1 bank 0 bank 1 intc ? mfi ? ctrl lvrc un?sed ?? h ?4 h un?sed un?sed eea eed eec data ram 40 h 9 fh ht66f24d special purpose data memory structure
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?? ???? ??? ?01? rev. 1.00 ? 7 ???? ??? ? 01 ? 00h iar 0 01h bank 0 mp 0 0?h iar 1 03h mp 1 04h 05h acc 0?h pcl 07h tblp 08h tblh 09h tbhp 0 ah status 0 bh smod 0 ch lvdc 0 dh integ 0 eh wdtc 0 fh tbc 10h intc 0 11h intc 1 1?h 19h papu 18h pawu 1 bh 1 ah 1 dh 1 ch 1 fh ?0h ?1h pa pac pbpu pb pbc 1 eh pcpu pc pcc ?5 h ?7 h ?9 h adrh ?8 h adrl ? bh ? ah ? ch adcr 0 adcr 1 acerl ? dh 35 h tm 1c1 34 h tm 1c0 3? h 38 h tm 1 dh 37 h tm 1 dl 3 ah tm 1 ah 39 h tm 1 al 3 bh 3 ch 3 dh un?sed 3 eh 3 fh bp 13h 14h mfi 0 15h mfi 1 1?h 17h ?? h ?3 h ?4 h pdpu pd pdc ? fh tm 0c1 ? eh tm 0c0 30 h 3? h tm 0 dh 31 h tm 0 dl tm 0 ah 33 h tm 0 al : un?sed ? read as 00 h tm 1c? tm 1 bh tm 1 bl bank 1 bank 0 bank 1 intc ? mfi ? ctrl lvrc prm 0 tmpc 0 ?? h un?sed un?sed eea eed eec data ram 40 h ffh HT66F25D special purpose data memory structure
rev. 1.00 ? 8 ???? ??? ? 01 ? rev. 1.00 ?9 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D special function register description most of the special function register details will be described in the relevant functional section. however, several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specified. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the mem ory location specifed by their corresponding memory pointers, mp0 or mp1. as the indirec t addressing re gisters are not physi cally i mplemented, rea ding t he indirec t addressing registers indirectly will return a result of 00h and writing to the registe rs indirectly will result in no operation. memory pointers C mp0, mp1 two me mory po inters, k nown a s mp0 a nd mp1 a re p rovided. t hese me mory po inters a re physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is di rected to is the address specifed by the relat ed memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register . direct addressing can only be used with bank 0 while all other banks must be addressed indirectly using mp1 and iar1. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data . section d ata adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code . section at 0 code org 0 0h begin: mov a, 04h ; setup size of block mov b lock, a mov a , offset adres1 ; accumulator loaded with frst ram address mov m p0, a ; setup memory pointer with frst ram address loop: clr i ar0 ; clear the data at address defned by mp0 inc m p0 ; increment memory pointer sdz b lock ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?8 ???? ??? ?01? rev. 1.00 ? 9 ???? ??? ? 01 ? bank pointer C bp selecting the required data memory area is achieved using the bank pointer . the bank pointer bp bit 0 is used to select data memory banks 0~1. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaf fected. it should be noted that the special function data memory is not af fected by t he ba nk se lection, whi ch m eans t hat t he spe cial func tion re gisters c an be a ccessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer . accessing data from banks other than bank 0 must be implemented using indirect addressing. bp register bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7~1 unimplemented, read as 0 bit 0 dmbp0 : data memory bank pointer 0: bank 0 1: bank 1 accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, whe n t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location. however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted.
rev. 1.00 30 ???? ??? ? 01 ? rev. 1.00 31 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. ? pdf is cleared by a system power-up or executing the "clr wdt" instruction. pdf is set by executing the "halt" instruction. ? to is cleared by a system power-up or executing the "clr wdt" or "halt" instruction. t o is set by a wdt time-out. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 30 ???? ??? ?01? rev. 1.00 31 ???? ??? ? 01 ? status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x ? nknown bit 7, 6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.00 3 ? ???? ??? ? 01 ? rev. 1.00 33 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D eeprom data memory the device contains an area of internal eeprom data memory . eeprom, which stands for electrically e rasable progra mmable re ad onl y me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. by incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . the avail ability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is 64x8 bits for this series of devices. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped into memory space and is there fore not directly addressable in the same way as the other types of memory . read and w rite operatio ns to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ht ?? f ? 4d ? 4 x 8 00h ~ 3fh ht ?? f ? 5d ? 4 x 8 00h ~ 3fh eeprom data memory structure eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register . the eec register however , being located in bank1, cannot be addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register , iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register , bp, set to the value, 01h, before any operations on the eec register are executed. ht66f24d/HT66F25D eeprom register list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d3 d ? d1 d0 eed d7 d ? d5 d4 d3 d ? d1 d0 eec wren wr rden rd eea register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5~0 data eeprom address bit 5 ~ bit 0
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 3? ???? ??? ?01? rev. 1.00 33 ???? ??? ? 01 ? eed register bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~0 unimplemented, read as 0 bit 3 wren : data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operation are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : data eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operation are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : data eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applicat ion program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.00 34 ???? ??? ? 01 ? rev. 1.00 35 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom the eeprom address of the data to be written must frst be placed in the eea register and the data placed in the eed regi ster. t o wri te data to the eeprom, the wri te enable bit, wren, in the eec register must frst be set high to enable the write function. after this, the wr bit in the eec register must be immediately set high to ini tiate a write cycle. these two instructions must be executed consecutively. the global interrupt bit emi should also frst be cleared before implementing any write operations, and then set again after the write cycle has started. note that setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal tim er whose operat ion is asynchronous to microcontrol ler syst em clock, a cert ain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fnished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero b y t he m icrocontroller, i nforming t he u ser t hat t he d ata h as b een wr itten t o t he e eprom. t he application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the bank pointer , bp , will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 34 ???? ??? ?01? rev. 1.00 35 ???? ??? ? 01 ? programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the w rite enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. programming examples reading data from the eeprom - polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer mov b p, a set i ar1.1 ; set rden bit, enable read operations set i ar1.0 ; start read cycle - set rd bit back: sz i ar1.0 ; check for read cycle end jmp b ack clr i ar1 ; disable eeprom read/write clr bp mov a , eed ; move read data to register mov r ead_data, a writing data to the eeprom - polling method mov a , eeprom_adres ; user defned address mov e ea, a mov a , eeprom_data ; user defned data mov e ed, a mov a , 040h ; setup memory pointer mp1 mov m p1, a ; mp1 points to eec register mov a , 01h ; setup bank pointer mov b p, a clr e mi set i ar1.3 ; set wren bit, enable write operations set i ar1.2 ; start write cycle - set wr bit - executed immediately ; after set wren bit set e mi back: sz i ar1.2 ; check for write cycle end jmp b ack clr i ar1 ; disable eeprom read/write clr bp
rev. 1.00 3 ? ???? ??? ? 01 ? rev. 1.00 37 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for t he w atchdog t imer a nd t ime b ase i nterrupts. e xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are pr ovided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. al l osc illator op tions are se lected t hrough t he c onfiguration o ptions. t he h igher f requency o scillators p rovide hi gher performance b ut c arry wi th i t t he d isadvantage o f h igher p ower r equirements, wh ile t he o pposite is of course true for the lower frequency osc illators. w ith the capabi lity of dynamicall y switching between fast and slow system clock, the device has the fexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. pins externa ? high speed cr ? sta ? hxt 400khz~1 ? mhz osc1/osc ? interna ? high speed rc hirc 4 ? 8 or 1 ? mhz externa ? low speed cr ? sta ? lxt 3 ? .7 ? 8 khz xt1/xt ? interna ? low speed rc lirc 3 ? khz oscillator types system clock confgurations there a re four syst em osc illators, t wo hi gh spe ed a nd t wo l ow spe ed osc illators. t he hi gh spe ed oscillators are the external crystal/ceramic oscillator C hxt and the internal rc oscillator - hirc. the low speed oscillators are the internal 32 khz oscillator C lirc and the external 32.768 khz crystal osc illator C l xt. se lecting whe ther t he l ow or hi gh spe ed osc illator i s use d a s t he syst em oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. the actual source clock used for each of the high speed and low speed oscillators is chosen via c onfiguration opt ions. t he frequenc y of t he sl ow spe ed or hi gh spe ed syst em c lock i s a lso determined usi ng t he hl clk bi t a nd cks2 ~ cks0 bi ts i n t he smod re gister. not e t hat t wo oscillator selection s must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 3? ???? ??? ?01? rev. 1.00 37 ???? ??? ? 01 ? hxt hirc f h ?- stage presca?er high speed osci??ator config?ration option hlclk ? cks ?~ cks 0 bits f h /? f h /4 f h /8 f h / 1? f h / 3? f h / ?4 f l f sub fast wake - ?p from sleep mode or idle mode contro? ( for hxt on?? ) f sys high speed osci??ator lirc lxt f sub osci??ator config?ration option system clock confgurations external crystal/ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is s elected via configuration option. f or mos t crystal os cillator configurations, the s imple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. however , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation.
? ? ?? crystal/resonator oscillator C hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 1 ? mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf note: c1 and c ? va ?? es are for g ? idance on ?? . crystal recommended capacitor values
rev. 1.00 38 ???? ??? ? 01 ? rev. 1.00 39 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D internal high speed rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming duri ng t he m anufacturing proc ess a nd t he i nclusion of i nternal fre quency c ompensation circuits are used to ensure that the infuence of the power supply volta ge, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will ha ve a t olerance wi thin 2%. not e t hat i f t his i nternal syst em c lock opt ion i s se lected, a s i t requires no external pins for its operation, i/o pins pa6 and pa5 are free fo r use as normal i/o pins. internal 32khz oscillator C lirc the int ernal 32khz syst em osc illator i s one of t he l ow fre quency osc illator c hoices, whi ch i s selected via conf guration option. it is a fully integrated rc os cillator w ith a typical frequency of 32 khz at 5v , requiring no external components for its implementation. device trimming during the m anufacturing p rocess a nd t he i nclusion o f i nternal f requency c ompensation c ircuits a re u sed to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25c degrees, the fxed oscillation frequency of 32 khz will have a tolerance within 10%. external 32.768khz crystal oscillator C lxt the e xternal 32.768khz cryst al syst em osc illator i s one of t he l ow fre quency osc illator c hoices, which is selected via confguration option. this clock source has a fxed frequency of 32.768 khz and requires a 32.768 khz crystal to be connected between pins xt1 and xt2. the external resistor and capa citor components connected to the 32.768 khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to dif ferent crystal manufacturing tolerances. during power -up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. howe ver, i n m any m icrocontroller a pplications i t may be ne cessary t o ke ep t he i nternal t imers ope rational e ven whe n t he m icrocontroller i s i n t he sleep or idle mode. t o do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to a dd t wo sm all v alue e xternal c apacitors, c 1 a nd c 2. t he e xact v alues o f c 1 a nd c 2 sh ould b e selected in consultation with the crystal or resonator manufacturer s specification. the external parallel feedback resistor, rp, is required. some confguration options determi ne if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. ? if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. ? if the lxt oscillator is used for any clock source, the 32.768 khz crystal should be connected to the xt1/xt2 pins.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 38 ???? ??? ?01? rev. 1.00 39 ???? ??? ? 01 ?
? ? ? ? ? ?- ? ? ? external lxt oscillator lxt oscillator c1 and c2 values crystal frequency c1 c2 3 ? .7 ? 8khz 10pf 10pf note:1. c1 a nd c ? va ?? es are for g ? idance on ?? . ? . r p =5m~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 q ? ick start 1 low-power after power on, the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly . however , after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it sh ould b e n oted t hat n o m atter wh at c ondition t he l xtlp b it i s se t t o, t he l xt o scillator wi ll always function normally , the only dif ference is that it will take more time to start up if in the low- power mode. supplementary oscillator the low s peed os cillator, in addition to providing a s ystem clock s ource, is als o us ed to provide a clock source to the t ime base interrupts function.
rev. 1.00 40 ???? ??? ? 01 ? rev. 1.00 41 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce ve rsa, l ower spe ed c locks re duce current consumption. as holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the us er w ith a w ide range of clock options us ing conf guration options and regis ter programming, a clock system can be confgured to obtain maximum application performance. the m ain sy stem c lock c an c ome f rom a h igh f requency f h o r l ow f requency f l so urce a nd i s se lected using the hlclk bit and cks2~cks0 bits in the smod register . the high speed system clock can be sourced from either a hxt or hirc oscillator , selected via a confguration option. the low speed system clock source can be sourced from internal clock f l . if f l is selec ted, then it can be sourced by the lirc oscillato r. the other choice, which is a divided version of the high speed system oscillator has a r ange o f f h /2~f h /64.note t hat wh en t he sy stem c lock so urce f sys i s swi tched t o f l f rom f h , the high speed oscillation will stop to conserve the power . thus there is no f h ~f h /64 for peripheral circuit to use. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . these internal clocks are sourced by the lirc or lxt oscillator . the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. the f tbc clock is used as a source for the t ime base interrupt functions and for the tms. hxt hirc lirc low speed osci??ator f h ?- stage presca?er high speed osci??ator config?ration option hlclk ? cks ?~ cks 0 bits f h /? f h /4 f h /8 f h / 1? f h / 3? f h / ?4 f sub fast wake - ?p from sleep or idle mode contro? ( for hxt on?? ) f sys lxt high speed osci??ator low speed osci??ator config?ration option f sys /4 time base f tb tbck f tbc watchdog timer f s
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 40 ???? ??? ?01? rev. 1.00 41 ???? ??? ? 01 ? system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. there are two modes all owing normal operati on of the microcontroller, t he normal mode a nd sl ow mode . t he re maining four m odes, t he sl eep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched of f to conserve power. operating mode description cpu f sys f sub f s f tbc normal mode on f h ~ f h / ? 4 on on on slow mode on f l on on on idle0 mode off off on on on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register . although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from the low speed osci llator lirc. running the micro controller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when a hal t instruction is executed and the idlen bit in the smod register is low . in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the w atchdog t imer function is disabled. in this mode, the lvden is must set to 0. if the lvden is set to 1, it wont enter the sleep0 mode. sleep1 mode the sleep mode is entered when a hal t instruction is executed and the idlen bit in the smod register is low . in the sleep1 mode the cpu will be stopped. however , the f sub and f s clocks will continue t o op erate i f t he l vden i s se t t o 1 or t he w atchdog t imer fu nction i s e nabled a nd i f i ts clock source is chosen via confguration option to come from the f sub .
rev. 1.00 4 ? ???? ??? ? 01 ? rev. 1.00 43 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D idle0 mode the idle0 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low . in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the w atchdog t imer, tms and sim. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the w atchdog t imer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4, then the f s clock will be of f, and if the source comes from f sub then f s will be on. idle1 mode the idle1 mode is entered when a hal t instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the w atchdog t imer, tms and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillato r. in the idle1 mode the w atchdog t imer clock, f s , will be on. if the source is f sys /4, then the f s clock will be on, and if the source comes from f sub then f s will be on. control register the corresponding system control registers, smod and ctrl, are used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks ? cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 : the system clock selection when hlclk is 0 000: f sub (f lxt or f lirc ) 001: f sub (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which is the lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 : fast w ake-up control (only for hxt) 0: disable 1: enable this i s t he fa st w ake-up c ontrol b it wh ich d etermines i f t he f sub c lock so urce i s initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temp orary system clock to provide a faster wake up time as the f sub clock is available.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 4? ???? ??? ?01? rev. 1.00 43 ???? ??? ? 01 ? bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscilla tor ready fag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1~2 clock cycles if the lirc oscillator is used and 128 clock cycles if the lxt oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready this i s t he hi gh spe ed syst em osc illator re ady fl ag whi ch i ndicates whe n t he hi gh speed system oscillator is stable. this fag is cleared to 0 by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefor e this fag will always be read as 1 by the application program after device power -on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 128 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the hal t instruction is executed. if this bit is high, when a hal t instruction is executed the device wi ll e nter t he i dle mo de. i n t he i dle1 mo de t he c pu wi ll st op r unning but the system clock will continue to keep the peripheral functions operational as the fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a hal t instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f sub 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock, the f h clock will be automatically switched off to conserve power. name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6~3 : unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program.
rev. 1.00 44 ???? ??? ? 01 ? rev. 1.00 45 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to re sume. t o e nsure t he de vice i s up a nd runni ng a s fa st a s possi ble a fa st w ake-up func tion i s provided, which allows f , namel y either the lxt or lirc oscillator , to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast w ake-up function is f , the fast w ake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast w ake-up function has no ef fect because the f clock is stopped. the fast w ake-up enable/ disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock and the fast w ake-up function is e nabled, t hen i t wi ll t ake o ne t o t wo t c lock c ycles o f t he l irc o r l xt o scillator f or t he sy stem to wa ke-up. t he sy stem wi ll t hen i nitially r un u nder t he f c lock sou rce u ntil 1 28 hxt c lock cycles have elapse d, at which point the ht o fag will switch high and the system will switch over to operating from the hxt oscillator. if the hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the hirc or 1~2 cycles of the lirc oscillator to wake up the system from the sleep or idle0 mode. the fast w ake-up bit, fsten will have no effect in these cases. system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1 ? 8 hxt c ? c ? es 1 ? 8 hxt c ? c ? es 1~ ? hxt c ? c ? es 1 1 ? 8 hxt c ? c ? es 1~ ? f sub c ? c ? es (system runs frst with f sub for 1 ? 8 hxt c ? c ? es a nd then switches over to r ? n with the hxt c ? ock) 1~ ? hxt c ? c ? es hirc x 15~1 ? hirc c ? c ? es 15~1 ? hirc c ? c ? es 1~ ? hirc c ? c ? es lirc x 1~ ? lirc c ? c ? es 1~ ? lirc c ? c ? es 1~ ? lirc c ? c ? es lxt x 1 ? 8 lxt c ? c ? es 1 ? 8 lxt c ? c ? es 1~ ? lxt c ? c ? es wake-up times x: dont care note that if the w atchdog t imer is disabled, which means that the lirc oscillator is of f, then there will be no fast w ake-up function available when the device wakes-up from the sleep0 mode.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 44 ???? ??? ?01? rev. 1.00 45 ???? ??? ? 01 ?

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? operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent tas k in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the hal t instruction. when a hal t instructio n is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~ f h /64 or f l . if the clock is from the f l , the high speed clock source will stop running to conserve power . when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may af fect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes.
rev. 1.00 4 ? ???? ??? ? 01 ? rev. 1.00 47 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes more power , the system clock can switch to run in the slow mode by set the hlclk bit to 0 and set the cks2~cks0 bits to 000b or 001b in the smod register . this will then use the low speed system oscillator which will consume less power . users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register.
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a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 4? ???? ??? ?01? rev. 1.00 47 ???? ??? ? 01 ? slow mode to normal mode switching in slow mode the system uses the lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 but cks2~cks0 is set to 010b, 01 1b, 100b, 101b, 1 10b or 1 11b. as a certain amount of time will be required for the high frequency clock to stabili se, the status of the ht o bit is checked. the amount of time required for high speed system oscillat or stabilization depends upon which high speed system oscillator type is used.
? ? ? ? ? ? ?? ?? ? -?? ? ? ? ? ?? ?? ? -?? ? ? ? ? ? ?? ?? ? -??? ? ? ? ? ?? ?? ? -?? ? entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 0 and the wdt and l vd both of f. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, wdt clock and t ime base clock will be stopped and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and stopped. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
rev. 1.00 48 ???? ??? ? 01 ? rev. 1.00 49 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the hal t instruction i n t he a pplication p rogram wi th t he i dlen b it i n smod r egister e qual t o 0 a nd t he w dt or l vd on. when this instruction is executed under the conditions described above, the following will occur: ? the system clock and t ime base clock will be stopped and the application program will stop at the halt instruction, but the wdt or lvd will remain with the clock source coming from the f lirc clock. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting as the wdt function is enabled. ? the i/o ports will maintain their present conditions. in slow mode the system uses the lirc low speed system oscillator . t o switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to 1 or hlclk bit is 0 but cks2~cks0 is set to 010b, 01 1b, 100b, 101b, 1 10b or 1 11b. as a certain amount of time will be required for the high frequency clock to stabili se, the status of the ht o bit is checked. the amount of time required for high speed system oscillat or stabilization depends upon which high speed system oscillator type is used. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in the ctrl register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the halt instruction, but the t ime base clock and f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt function is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction in the application program with the idlen bit in smod register equal to 1 and the fsyson bit in the ctrl register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the system clock, t ime base clock and f sub clock will be on and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt function is enabled. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 48 ???? ??? ?01? rev. 1.00 49 ???? ??? ? 01 ? standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or the lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. if a wdt time-out occurs, it will set t o fag and cause a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the instruction following the hal t instruction. if the system is woken up by an interrupt, then two possible situations may occur . the first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the hal t instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the relate d interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter . for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an of f state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after the ht o bit is set to 1. at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator . the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the frst instruction is executed.
rev. 1.00 50 ???? ??? ? 01 ? rev. 1.00 51 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from the hxt oscillator and the fsten bit is set to 1, the system clock can frst be switched to the lxt or lirc oscillator after wake up. there are peripheral functions, such as wdt and tms, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the periphera l functions mentioned above will change accordingly. the on/of f condition of f sub and f s depends upon whether the wdt is enabled or disabled as the f sub clock source is selected from f lirc . watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is provided by the internal clock, f s , which is in turn supplied by the lirc oscillato r. the lirc internal oscillator has an approximate period of 32 khz at a supply voltage of 5v . however , it should be noted that this specifed internal clock period can vary with vdd, tem perature and process variations. the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer tim eouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the w atchdog t imer. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we ? we1 we0 ws ? ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~3 : wdt function software control if the wdt confguration option is always enable: 10101 or 01010: enabled other: reset mcu if the wdt confguration option is controlled by the wdt control register: 10101: disabled 01010: enabled other: reset mcu when these bits are changed by the environmental noise to reset the microcontroller , the reset operation will be activated after 2~3 lirc clock cycles and the wrf bit in the ctrl register will be set to 1.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 50 ???? ??? ?01? rev. 1.00 51 ???? ??? ? 01 ? bit 2~0 ws2~ws0 : wdt t ime-out period selection 000: 2 8 /f s 001: 2 10 /f s 010: 2 12 /f s 011: 2 14 /f s 100: 2 15 /f s 101: 2 16 /f s 110: 2 17 /f s 111: 2 18 /f s t bt name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f sys control in idle mode describe elsewhere. bit 6~3 : unimplemented, read as 0 bit 2 lvrf : lvr function reset fag describe elsewhere. bit 1 lrf : lvr control register software reset fag describe elsewhere. bit 0 wrf : wdt control register software reset fag 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the cle ar watchdog instructions. if the program malfunction s for whatever reason, jumps to an unknow n location, or enters an endles s loop, these clear ins tructions w ill not be executed in the correct manner , in which case the w atchdog t imer will overfow and reset the device. some of t he w atchdog t imer opt ions, suc h as al ways on se lect and cl ear i nstruction t ype are se lected using configuration options. w ith regard to the w atchdog t imer enable/disable function, there are a lso fi ve bi ts, w e4~we0, i n t he w dtc re gister t o of fer a dditional e nable/disable a nd re set control of the w atchdog t imer. if the wdt configuration option is determined that the wdt function is always enabled, the we4~we0 bits still have ef fects on the wdt function. when the we4~we0 bits value is equal to 01010b or 10101b, the wdt function is enabled. however , if the we4~we0 bits are changed to any other values except 01010b and 10101b, which is caused by the environmental noise, it will reset the microcontroller after 2~3 lirc clock cycles. if the wdt confguration option is determined that the wdt function is controlled by the wdt control register , the we4~we0 values can determine which mode the wdt operates in. the wdt function will be disabled when the we4~we0 bits are set to a value of 10101b. the wdt function will be enabled if the we4~we0 bits value is equal to 01010b. if the we4~we0 bits are set to any other values by the environmental noise, except 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have the value of 01010b.
rev. 1.00 5 ? ???? ??? ? 01 ? rev. 1.00 53 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D watchdog timer enable/disable control wdt confguration option we4 ~ we0 bits wdt function a ? wa ? s enab ? e 01010b or 10101b enab ? e an ? other va ?? e reset mcu contro ?? ed b ? wdt contro ? register 10101b disab ? e 01010b enab ? e an ? other va ?? e reset mcu x: dont care. under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt reset, which means a certain value except 01010b and 10101b written into the we4~we0 bit fled, the second is using the w atchdog t imer software clear instructions and the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt . the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. " clr wdt " instr?ction 8- stage divider wdt presca?er we 4~ we0 bits wdtc register reset mcu f s f sub f s /? 8 8- to - 1 mux clr ws ?~ ws 0 (f s /? 8 ~ f s /? 18 ) wdt time - o?t (? 8 /f s ~ ? 18 /f s ) watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in different register conditions being setup. another reset exists in the form of a low v oltage reset, l vr, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 5? ???? ??? ?01? rev. 1.00 53 ???? ??? ? 01 ? reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally: power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart note: t rstd is power-on delay, typical time=50ms low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr func tion is always enabled with a specifc l vr voltag e v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the ctrl register will also be set to 1. for a valid l vr signal, a low supply voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for a time greater than that specifed by t lvr in the a.c. characteristics. if the low supply voltag e state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. the actual v lvr value can be selected by the l vs bits in the l vrc register. if the l vs7~lvs0 bits are changed to some certain values by the environmental noise, the lvr will reset the device after 2~3 lirc clock cycles. when this happens, the lrf bit in the ctrl register will be set to 1. after power on the register will have the value of 01010101b. note that the lvr function will be automatically disabled when the device enters the power down mode. low voltage reset timing chart note: t rstd is power-on delay, typical time=100ms
rev. 1.00 54 ???? ??? ? 01 ? rev. 1.00 55 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs ? lvs5 lvs4 lvs3 lvs ? lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 7~0 lvs7~lvs0 : lvr v oltage select control 01010101: 2.1v 00110011: 2.55v 10011001: 3.15v 10101010: 3.8v any other value : generates mcu reset when an actual low voltage condition occurs, as specifed by one of the four defned lvr v oltage v alues a bove, a n mc u r eset wi ll b e g enerated. i n t his si tuation t he register contents will remain the same after such a reset occurs. any register value, other than the four defned l vr values above, will also result in the generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation the register contents will be reset to the por value. ? ctrl register bit 7 6 5 4 3 2 1 0 name fsyson lvrf lrf wrf r/w r/w r/w r/w r/w por 0 x 0 0 bit 7 fsyson : f control in idle mode describe elsewhere. bit 6~3 : unimplemented, read as 0 bit 2 lvrf : lvr function reset fag 0: not occur 1: occurred this bit is set to 1 when a specifc low v oltage reset situation condition occurs. this bit can only be cleared to 0 by the application program. bit 1 lrf : lvr control register software reset fag 0: not occur 1: occurred this bit is set to 1 if the l vrc register contains any non defned l vr voltage register values. this in ef fect acts like a software reset function. t his bit can only be cleared to 0 by the application program. bit 0 wrf : wdt control register software reset fag describe elsewhere. watchdog time-out reset during normal operation the w atchdog t ime-out re set duri ng norm al op eration wi ll pe rform a ful l re set a nd a lso t h e watchdog time-out fag t o will be set to 1. wdt time-out reset during normal operation timing chart note: t rstd is power-on delay, typical time=16.7ms
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 54 ???? ??? ?01? rev. 1.00 55 ???? ??? ? 01 ? watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the sst is 128 clock cycles for hxt. the sst is 1~2 clock cycles for lirc. reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset ? ? lvr reset d ? ring normal or slow mode operation 1 ? wdt time-o ? t reset d ? ring normal or slow mode operation 1 1 wdt time-o ? t reset d ? ring idle or sleep mode operation note: ? stands for ? nchanged. the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after power-on reset program co ? nter reset to zero interr ? pts a ?? interr ? pt wi ?? be disab ? ed wdt ? time base c ? ear after reset ? wdt begins co ? nting timer mod ?? es timer co ? nter wi ?? be t ? rned off inp ? t/o ? tp ? t ports i/o ports wi ?? be set ? p as inp ? ts and an0~an7 as a/d inp ? t pins stack pointer stack pointer wi ?? point to the top of the stack
rev. 1.00 5 ? ???? ??? ? 01 ? rev. 1.00 57 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. ht66f24d register power on reset lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- --- ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- -xxx ---- - ??? ---- - ??? ---- - ??? status --00 xxxx -- ?? ???? --1 ? ???? --11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc --00 -000 --00 -000 --00 -000 -- ?? - ??? lvrc 0101 0101 ???? ???? 0101 0101 ???? ???? ctrl 0--- -x00 0--- -100 0--- -000 ? --- - ??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? wdtc 0101 0011 0101 0011 0101 0011 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? ---0 ---0 ---0 ---0 ---0 ---0 --- ? --- ? mfi0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi1 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi ? --00 --00 --00 --00 --00 --00 -- ?? -- ?? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu --00 0000 --00 0000 --00 0000 -- ?? ???? pb --11 1111 --11 1111 --11 1111 -- ?? ???? pbc --11 1111 --11 1111 --11 1111 -- ?? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? prm0 0000 ---- 0000 ---- 0000 ---- ???? ---- tmpc0 --00 0000 --00 0000 --00 0000 -- ?? ???? adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- ???? adcr0 0110 -000 0110 -000 0110 -000 ???? - ???
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 5? ???? ??? ?01? rev. 1.00 57 ???? ??? ? 01 ? register power on reset lvr reset wdt time-out (normal operation) wdt time-out (idle) adcr1 00-0 -000 00-0 -000 00-0 -000 ?? - ? - ??? acerl 1111 1111 1111 1111 1111 1111 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.00 58 ???? ??? ? 01 ? rev. 1.00 59 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D HT66F25D register power on reset lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? mp1 xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? bp ---- ---0 ---- ---0 ---- ---0 ---- --- ? acc xxxx xxxx ???? ???? ???? ???? ???? ???? pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx ???? ???? ???? ???? ???? ???? tblh xxxx xxxx ???? ???? ???? ???? ???? ???? tbhp ---- xxxx ---- ???? ---- ???? ---- ???? status --00 xxxx -- ?? ???? --1 ? ???? --11 ???? smod 0000 0011 0000 0011 0000 0011 ???? ???? lvdc --00 -000 --00 -000 --00 -000 -- ?? - ??? lvrc 0101 0101 ???? ???? 0101 0101 ???? ???? ctrl 0--- -x00 0--- -100 0--- -000 ? --- - ??? integ ---- 0000 ---- 0000 ---- 0000 ---- ???? wdtc 0101 0011 0101 0011 0101 0011 ???? ???? tbc 0011 0111 0011 0111 0011 0111 ???? ???? intc0 -000 0000 -000 0000 -000 0000 - ??? ???? intc1 0000 0000 0000 0000 0000 0000 ???? ???? intc ? ---0 ---0 ---0 ---0 ---0 ---0 --- ? --- ? mfi0 --00 --00 --00 --00 --00 --00 -- ?? -- ?? mfi1 -000 -000 -000 -000 -000 -000 - ??? - ??? mfi ? --00 --00 --00 --00 --00 --00 -- ?? -- ?? pawu 0000 0000 0000 0000 0000 0000 ???? ???? papu 0000 0000 0000 0000 0000 0000 ???? ???? pa 1111 1111 1111 1111 1111 1111 ???? ???? pac 1111 1111 1111 1111 1111 1111 ???? ???? pbpu 0000 0000 0000 0000 0000 0000 ???? ???? pb 1111 1111 1111 1111 1111 1111 ???? ???? pbc 1111 1111 1111 1111 1111 1111 ???? ???? pcpu 0000 0000 0000 0000 0000 0000 ???? ???? pc 1111 1111 1111 1111 1111 1111 ???? ???? pcc 1111 1111 1111 1111 1111 1111 ???? ???? pdpu ---- --00 ---- --00 ---- --00 ---- -- ?? pd ---- --11 ---- --11 ---- --11 ---- -- ?? pdc ---- --11 ---- --11 ---- --11 ---- -- ?? prm0 0000 ---- 0000 ---- 0000 ---- ???? ---- tmpc0 0000 0000 0000 0000 0000 0000 ???? ???? adrl (adrfs=0) xxxx ---- xxxx ---- xxxx ---- ???? ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=0) xxxx xxxx xxxx xxxx xxxx xxxx ???? ???? adrh (adrfs=1) ---- xxxx ---- xxxx ---- xxxx ---- ???? adcr0 0110 -000 0110 -000 0110 -000 ???? - ??? adcr1 00-0 -000 00-0 -000 00-0 -000 ?? - ? - ???
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 58 ???? ??? ?01? rev. 1.00 59 ???? ??? ? 01 ? register power on reset lvr reset wdt time-out (normal operation) wdt time-out (idle) acerl 1111 1111 1111 1111 1111 1111 ???? ???? tm0c0 0000 0000 0000 0000 0000 0000 ???? ???? tm0c1 0000 0000 0000 0000 0000 0000 ???? ???? tm0dl 0000 0000 0000 0000 0000 0000 ???? ???? tm0dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm0al 0000 0000 0000 0000 0000 0000 ???? ???? tm0ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1c0 0000 0000 0000 0000 0000 0000 ???? ???? tm1c1 0000 0000 0000 0000 0000 0000 ???? ???? tm1c ? 0000 0000 0000 0000 0000 0000 ???? ???? tm1dl 0000 0000 0000 0000 0000 0000 ???? ???? tm1dh ---- --00 ---- --00 ---- --00 ---- -- ?? tm1al 0000 0000 0000 0000 0000 0000 ???? ???? tm1ah ---- --00 ---- --00 ---- --00 ---- -- ?? tm1bl 0000 0000 0000 0000 0000 0000 ???? ???? tm1bh ---- --00 ---- --00 ---- --00 ---- -- ?? note: u stands for unchanged x stands for unknown - stands for unimplemented
rev. 1.00 ? 0 ???? ??? ? 01 ? rev. 1.00 ?1 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the de vice prov ides bi directional i nput/output l ines l abeled wi th por t na mes p a~pd. t hese i/ o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. a ll of thes e i/o ports can be used for input and output operations. for input operation, these ports are non-latch ing, which means the inputs must be ready at the t2 rising edge of instruction mov a,[m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o resistor lists ht66f24d register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 papu papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 pac pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 pa pa7 pa ? pa5 pa4 pa3 pa ? pa1 pa0 pbpu pbpu5 pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 pb pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 pbc pb5 pb4 pb3 pb ? pb1 pb0 pcpu pcpu7 pcpu ? pcpu5 pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 pc pcc7 pcc ? pcc5 pcc4 pcc3 pcc ? pcc1 pcc0 pcc pc7 pc4 pc5 pc4 pc3 pc ? pc1 pc0 HT66F25D register name bit 7 6 5 4 3 2 1 0 pawu pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 papu papu7 papu ? papu5 papu4 papu3 papu ? papu1 papu0 pac pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 pa pa7 pa ? pa5 pa4 pa3 pa ? pa1 pa0 pbpu pbpu7 pbpu ? pbpu5 pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 pb pbc7 pbc ? pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 pbc pb7 pb ? pb5 pb4 pb3 pb ? pb1 pb0 pcpu pcpu7 pcpu ? pcpu5 pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 pc pcc7 pcc ? pcc5 pcc4 pcc3 pcc ? pcc1 pcc0 pcc pc7 pc4 pc5 pc4 pc3 pc ? pc1 pc0 pdpu pdpu1 pdpu0 pd pdc1 pdc0 pdc pd1 pd0
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?0 ???? ??? ?01? rev. 1.00 ? 1 ???? ??? ? 01 ? pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high re sistors a re se lected usi ng re gisters p ap u~pdpu a nd a re i mplemented usi ng we ak pmos transistors. papu register bit 7 ? 5 4 3 ? 1 0 name pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 pawu7~pawu0: i/o port a bit 7 ~ bit 0 pull-high control 0: disable 1: enable pbpu register ? ht66f24d bit 7 ? 5 4 3 ? 1 0 name pbpu5 pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 ? HT66F25D bit 7 ? 5 4 3 ? 1 0 name pbpu7 pbpu ? pbpu5 pbpu4 pbpu3 pbpu ? pbpu1 pbpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 : unimplemented, read as 0 pbpun : i/o port b bit n pull-high control 0: disable 1: enable pcpu register ? ht66f24d/HT66F25D bit 7 ? 5 4 3 ? 1 0 name pcpu7 pcpu ? pcpu5 pcpu4 pcpu3 pcpu ? pcpu1 pcpu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 : unimplemented, read as 0 pcpun : i/o port c bit n pull-high control 0: disable 1: enable
rev. 1.00 ?? ???? ??? ? 01 ? rev. 1.00 ?3 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D pdpu register - HT66F25D only bit 7 ? 5 4 3 ? 1 0 name pdpu1 pdpu0 r/w r/w r/w por 0 0 : unimplemented, read as 0 pdpun : i/o port d bit n pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 ? 5 4 3 ? 1 0 name pawu7 pawu ? pawu5 pawu4 pawu3 pawu ? pawu1 pawu0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7 ~ bit 0 w ake-up control 0: disable 1: enable i/o port control registers each i/o port has its ow n control register known as p ac~pdc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still b e u sed t o r ead t he o utput r egister. ho wever, i t sh ould b e n oted t hat t he p rogram wi ll i n f act only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 ? 5 4 3 ? 1 0 name pac7 pac ? pac5 pac4 pac3 pac ? pac1 pac0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 pac7~pac0 : i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?? ???? ??? ?01? rev. 1.00 ? 3 ???? ??? ? 01 ? pbc register ? ht66f24d bit 7 ? 5 4 3 ? 1 0 name pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 ? HT66F25D bit 7 ? 5 4 3 ? 1 0 name pbc7 pbc ? pbc5 pbc4 pbc3 pbc ? pbc1 pbc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 : unimplemented, read as 0 pbcn : i/o port b bit n input/output control 0: output 1: input pcc register ? ht66f24d/HT66F25D bit 7 ? 5 4 3 ? 1 0 name pcc7 pcc ? pcc5 pcc4 pcc3 pcc ? pcc1 pcc0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 : unimplemented, read as 0 pccn : i/o port c bit n input/output control 0: output 1: input pdc register - HT66F25D only bit 7 ? 5 4 3 ? 1 0 name pdc1 pdc0 r/w r/w r/w por 1 1 bit 7~2 unimplemented, read as 0 bit 1~0 pdc1~pdc0 : i/o port d bit 1 ~ bit 0 input/output control 0: output 1: input
rev. 1.00 ? 4 ???? ??? ? 01 ? rev. 1.00 ?5 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. t he wa y i n which the pin function of each pin is selected is dif ferent for each function and a priority order is established whe re m ore t han one pi n func tion i s se lected si multaneously. addi tionally t here i s a prm0 register to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. the devices include a prm0 register which can select the functions of certain pins. prm0 register bit 7 ? 5 4 3 ? 1 0 ht ?? f ? 4d ht ?? f ? 5d int1ps int0ps tck1ps tck0ps pin-remapping register list ht66f24d/HT66F25D bit 7 ? 5 4 3 ? 1 0 name int1ps int0ps tck1ps tck0ps r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 int1ps : int1 pin remapping control 0: int1 on pb0 1: int1 on pc1 bit 6 int0ps : int0 pin remapping control 0: int1 on pa2 1: int1 on pc0 bit 5 tck1ps : tck1 pin remapping control 0: tck1 on pb0 1: tck1 on pc3 bit 5 unimplemented, read as 0 bit 4 tck0ps : tck0 pin remapping control 0: tck0 on pa6 1: tck0 on pc2 bit 3~0 unimplemented, read as 0
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?4 ???? ??? ?01? rev. 1.00 ? 5 ???? ??? ? 01 ? i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logi cal construc tion of the i/ o pi n will di ffer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin- shared structures does not permit all types to be shown. the diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins.

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rev. 1.00 ?? ???? ??? ? 01 ? rev. 1.00 ?7 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pdc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port dat a regi sters, p a~pd, a re frst progra mmed. se lecting whi ch pi ns a re i nputs and whi ch are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol re gister u sing t he set [m ].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions each device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two o r t hree i ndividual i nterrupts. t he a ddition o f i nput a nd o utput p ins f or e ach t m e nsures t hat users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devic es conta in up to two tms with each tm having a reference name of tm0 and tm1. each individual tm ca n be ca tegorised as a ce rtain type , nam ely compa ct t ype tm (ctm), st andard type tm (stm) or enhanced t ype tm (etm). although similar in nature, the dif ferent tm types vary i n t heir f eature c omplexity. t he c ommon f eatures t o a ll o f t he c ompact, st andard a nd e nhanced tms will be described in this sectio n and the detailed operation regarding each of the tm types will be described in separate sections. the main features and dif ferences between the three types of tms are summarised in the accompanying table. function ctm stm etm timer/co ? nter i/p capt ? re compare match o ? tp ? t pwm channe ? s 1 1 ? sing ? e p ?? se o ? tp ? t 1 ? pwm a ? ignment edge edge edge & centre pwm adj ? stment period & d ? t ? d ? t ? or period d ? t ? or period d ? t ? or period tm function summary
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?? ???? ??? ?01? rev. 1.00 ? 7 ???? ??? ? 01 ? each device in the series contains a specifc number of either compact t ype, standard t ype and enhanced t ype tm units which are shown in the table together with their individual reference name, tm0~tm1. device tm0 tm1 ht ?? f ? 4d 10-bit ctm 10-bit stm ht ?? f ? 5d 10-bit ctm 10-bit etm tm name/type reference tm operation the three dif ferent types of tm of fer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the high speed clock f h , the ftbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in ef fect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p , which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin.
rev. 1.00 ? 8 ???? ??? ? 01 ? rev. 1.00 ?9 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the p wm output w aveform. a s the tm output pins are pin-s hared w ith other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is dif ferent, the details are provided i n t he a ccompanying t able. al l t m out put pi n nam es ha ve a _n suffx. pin nam es t hat include a _1 or _2 suffx indica te that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. device ctm stm etm register ht ?? f ? 4d tp0_0 ? tp0_1 ? tp0_ ? tp1_0 ? tp1_1 ? tp1_ ? tmpc0 ht ?? f ? 5d tp0_0 ? tp0_1 ? tp0_ ? tp1a_0 ? tp1a_1 tp1b_0 ? tp1b_1 ? tp1b_ ? tmpc0 tm output pins tm input/output pin control registers selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. tmpc0 register device bit 7 6 5 4 3 2 1 0 ht ?? f ? 4d t1cp ? t1cp1 t1cp0 t0cp ? t0cp1 t0cp0 ht ?? f ? 5d t1acp1 t1acp0 t1bcp ? t1bcp1 t1bcp0 t0cp ? t0cp1 t0cp0 tm input/output pin control register list
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 ?8 ???? ??? ?01? rev. 1.00 ? 9 ???? ??? ? 01 ? pa7 output function 0 1 1 0 output pa6/tck1 tck input tm0 (ctm) pa7/tp0_2 t0cp2 pa0 output function 0 1 pa0 pa7 1 0 pa0/tp0_1 t0cp1 pa3 output function 0 1 pa3 1 0 pa3/tp0_0 t0cp0 pb1 output function 0 1 pb1 1 0 output capture input pb0/tck1 tck input 1 0 tm1 (stm) pb1/tp1_2 t1cp2 t1cp2 pa1 output function 0 1 pa1 1 0 1 0 pa1/tp1_1 t1cp1 t1cp1 pa4 output function 0 1 pa4 1 0 pa4/tp1_0 t1cp0 1 0 t1cp0 note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
rev. 1.00 70 ???? ??? ? 01 ? rev. 1.00 71 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D pa7 output function 0 1 1 0 output pa6/tck1 tck input tm0 (ctm) pa7/tp0_2 t0cp2 pa0 output function 0 1 pa0 pa7 1 0 pa0/tp0_1 t0cp1 pa3 output function 0 1 pa3 1 0 pa3/tp0_0 t0cp0 pb1 output function 0 1 pb1 1 0 ccrb output ccrb capture input pb0/tck1 tck input 1 0 tm1 (etm) pb1/tp1b_2 t1bcp2 t1bcp2 pa1 output function 0 1 pa1 1 0 1 0 pa1/tp1_1 t1bcp1 t1bcp1 pa4 output function 0 1 pa4 1 0 pa4/tp1b_0 t1bcp0 1 0 t1bcp0 pb2 output function 0 1 pb2 1 0 output capture input 1 0 pb2/tp1a_1 t1acp1 t1acp1 t1acp0 pa5 output function 0 1 pa5 1 0 1 0 pa5/tp1a_0 t1acp0 note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 70 ???? ??? ?01? rev. 1.00 71 ???? ??? ? 01 ? tmpc0 - ht66f24d register name bit 7 6 5 4 3 2 1 0 name t1cp ? t1cp1 t1cp0 t0cp ? t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1cp2 : tp1_2 pin enable control 0: disable 1: enable bit 4 t1cp1 : tp1_1 pin enable control 0: disable 1: enable bit 3 t1cp0 : tp1_0 pin enable control 0: disable 1: enable bit 2 t0cp2 : tp0_2 pin enable control 0: disable 1: enable bit 1 t0cp1 : tp0_1 pin enable control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin enable control 0: disable 1: enable
rev. 1.00 7 ? ???? ??? ? 01 ? rev. 1.00 73 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tmpc0 - HT66F25D register name bit 7 6 5 4 3 2 1 0 name t1acp1 t1acp0 t1bcp ? t1bcp1 t1bcp0 t0cp ? t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1acp1 : tp1a_1 pin enable control 0: disable 1: enable bit 6 t1acp0 : tp1a_0 pin enable control 0: disable 1: enable bit 5 t1bcp2 : tp1b_2 pin enable control 0: disable 1: enable bit 4 t1bcp1 : tp1b_1 pin enable control 0: disable 1: enable bit 3 t1bcp0 : tp1b_0 pin enable control 0: disable 1: enable bit 2 t0cp2 : tp0_2 pin enable control 0: disable 1: enable bit 1 t0cp1 : tp0_1 pin enable control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin enable control 0: disable 1: enable
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 7? ???? ??? ?01? rev. 1.00 73 ???? ??? ? 01 ? programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way . the important point to note is that data transfer to and from the 8-bit buffer and its rela ted low byte only takes place when a write or read operation to its corresponding high byte is executed. as the ccra and ccrb registers are impleme nted in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. data b?s 8- bit b?ffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm co?nter register ( read on?? ) tm ccra register ( read / write ) tm ccrb register ( read / write ) the following steps show the read and write procedures: writing data to ccrb or ccra ? step 1 . w rite data to low byte tmxal or tmxbl - note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah or tmxbh - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh - here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl - this step reads data from the 8-bit buffer.
rev. 1.00 74 ???? ??? ? 01 ? rev. 1.00 75 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D compact type tm C ctm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, t imer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or more external output pins. these external output pins can be the same signal or the inverse signal. ctm name tm no. tm input pin tm output pin ht ?? f ? 4d ht ?? f ? 5d 10-bit ctm 0 tck0 tp0_0 ? tp0_1 ? tp0_ ? compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 74 ???? ??? ?01? rev. 1.00 75 ???? ??? ? 01 ? compact type tm register description overall operat ion of t he compa ct tm i s c ontrolled usi ng si x regi sters. a rea d only regi ster pai r exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. ctm register list - ht66f24d / HT66F25D register name bit 7 6 5 4 3 2 1 0 tm0c0 t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d ? d5 d4 d3 d ? d1 d0 tm0dh d9 d8 tm0al d7 d ? d5 d4 d3 d ? d1 d0 tm0ah d9 d8 10-bit compact tm register list tm0dl register register name bit 7 6 5 4 3 2 1 0 tm0c0 d7 d ? d5 d4 d3 d ? d1 d0 tm0c1 r r r r r r r r tm0dl 0 0 0 0 0 0 0 0 bit 7~0 tm0dl : tm0 counter low byte register bit 7 ~ bit 0 tm0 10-bit counter bit 7 ~ bit 0 tm0dh register register name bit 7 6 5 4 3 2 1 0 tm0c0 d9 d8 tm0c1 r r tm0dl 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm0dh : tm0 counter high byte register bit 1 ~ bit 0 tm0 10-bit counter bit 9 ~ bit 8 tm0al register register name bit 7 6 5 4 3 2 1 0 tm0c0 d7 d ? d5 d4 d3 d ? d1 d0 tm0c1 r/w r/w r/w r/w r/w r/w r/w r/w tm0dl 0 0 0 0 0 0 0 0 bit 7~0 tm0al : tm0 ccra low byte register bit 7 ~ bit 0 tm0 10-bit ccra bit 7 ~ bit 0
rev. 1.00 7 ? ???? ??? ? 01 ? rev. 1.00 77 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tm0ah register register name bit 7 6 5 4 3 2 1 0 tm0c0 d9 d8 tm0c1 r/w r/w tm0dl 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm0ah : tm0 ccra high byte register bit 1 ~ bit 0 tm0 10-bit ccra bit 9 ~ bit 8 tm0c0 register register name bit 7 6 5 4 3 2 1 0 tm0c0 t0pau t0ck ? t0ck1 t0ck0 t0on t0rp ? t0rp1 t0rp0 tm0c1 r/w r/w r/w r/w r/w r/w r/w r/w tm0dl 0 0 0 0 0 0 0 0 bit 7 t0pau : tm0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2~t0ck0 : select tm0 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: undefned, can not be selected. 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 t0on : tm0 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 7? ???? ??? ?01? rev. 1.00 77 ???? ??? ? 01 ? bit 2~0 t0rp2~t0rp 0: tm0 ccrp 3-bit register, compare with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 0cclr bi t i s se t t o zero. set ting t he t 0cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tm0c1 register register name bit 7 6 5 4 3 2 1 0 tm0c0 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0c1 r/w r/w r/w r/w r/w r/w r/w r/w tm0dl 0 0 0 0 0 0 0 0 bit 7~6 t0m1~t0m0 : select tm0 operation mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t0m1 and t0m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0 : select tp0_0, tp0_1, tp0_2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running.
rev. 1.00 78 ???? ??? ? 01 ? rev. 1.00 79 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D in t he com pare ma tch out put mode , t he t 0io1 a nd t 0io0 bi ts de termine how t he tm out put pin change s sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch hi gh, switch low or to toggl e its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t0oc bit in the tm0c1 register . note that the output level requested by the t0io1 and t0io0 bits must be dif ferent from the initial value setup using the t0oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the tnio1 and tnio0 bits only after the tmn has been switched of f. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running bit 3 t0oc : tp0_0, tp0_1, tp0_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm is in the t imer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol : tp0_0, tp0_1, tp0_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0_0, tp0_1 or tp0_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t0dpx : tm0 pwm period/duty control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr : select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 78 ???? ??? ?01? rev. 1.00 79 ???? ??? ? 01 ? compact type tm operation modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t nm1 a nd t nm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00b respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
rev. 1.00 80 ???? ??? ? 01 ? rev. 1.00 81 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin time ccrp=0 ccrp > 0 co?nter overf?ow ccrp > 0 co?nter c?eared b? ccrp va??e pa?se res?me stop co?nter restart tncclr = 0; tnm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnoc=0 o?tp?t togg?e with tnaf f?ag note tnio [1:0] = 10 active high o?tp?t se?ect here tnio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 80 ???? ??? ?01? rev. 1.00 81 ???? ??? ? 01 ? co?nter va??e 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin time ccra=0 ccra = 0 co?nter overf?ow ccra > 0 co?nter c?eared b? ccra va??e pa?se res?me stop co?nter restart tncclr = 1; tnm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnoc=0 o?tp?t togg?e with tnaf f?ag note tnio [1:0] = 10 active high o?tp?t se?ect here tnio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol is high tnpf not generated no tnaf f?ag generated on ccra overf?ow o?tp?t does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.00 8 ? ???? ??? ? 01 ? rev. 1.00 83 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 5 ? 384 51 ? ? 40 7 ? 8 89 ? 10 ? 4 d ? t ? ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra = 128, the ctm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra d ? t ? 1 ? 8 ? 5 ? 384 51 ? ? 40 7 ? 8 89 ? 10 ? 4 the pwm output period cycle is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 8? ???? ??? ?01? rev. 1.00 83 ???? ??? ? 01 ? co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin (tnoc=1) time co?nter c?eared b? ccrp pa?se res?me co?nter stop if tnon bit ?ow co?nter reset when tnon ret?rns high tndpx = 0; tnm [1:0] = 10 pwm d?t? c?c?e set b? ccra pwm res?mes operation o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set b? ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 84 ???? ??? ? 01 ? rev. 1.00 85 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin (tnoc=1) time co?nter c?eared b? ccra pa?se res?me co?nter stop if tnon bit ?ow co?nter reset when tnon ret?rns high tndpx = 1; tnm [1:0] = 10 pwm d?t? c?c?e set b? ccrp pwm res?mes operation o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set b? ccra tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 84 ???? ??? ?01? rev. 1.00 85 ???? ??? ? 01 ? standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. stm name tm no. tm input pin tm output pin ht ?? f ? 4d 10-bit stm 1 tck1 tp1_0 ? tp1_1 ? tp1_ ? ht ?? f ? 5d standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
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rev. 1.00 8 ? ???? ??? ? 01 ? rev. 1.00 87 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. stm register list C ht66f24d register name bit 7 6 5 4 3 2 1 0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d ? d5 d4 d3 d ? d1 d0 tm1dh d9 d8 tm1al d7 d ? d5 d4 d3 d ? d1 d0 tm1ah d9 d8 10-bit standard tm register list tm1dl register register name bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7 ~ bit 0 tm1 10-bit counter bit 7 ~ bit 0 tm1dh register register name bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1 ~ bit 0 tm1 10-bit counter bit 9 ~ bit 8 tm1al register register name bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7 ~ bit 0 tm1 10-bit ccra bit 7 ~ bit 0
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 8? ???? ??? ?01? rev. 1.00 87 ???? ??? ? 01 ? tm1ah register register name bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1 ~ bit 0 tm1 10-bit ccra bit 9 ~ bit 8 tm1c0 register register name bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f tbc 101: undefned, can not be selected. 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run and clearing the bit disables the tm. clearing this bit to zero will stop t he c ounter f rom c ounting a nd t urn o ff t he t m wh ich wi ll r educe i ts p ower consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high.
rev. 1.00 88 ???? ??? ? 01 ? rev. 1.00 89 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compare with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value. tm1c1 register register name bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0 : select tm1 operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t1m1 and t1m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0 : select tp1_0, tp1_1, tp1_2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1_0, tp1_1, tp1_2 01: input capture at falling edge of tp1_0, tp1_1, tp1_2 01: input capture at falling/rising edge of tp1_0, tp1_1, tp1_2 11: input capture disabled timer/counter mode unused.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 88 ???? ??? ?01? rev. 1.00 89 ???? ??? ? 01 ? these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in t he com pare ma tch out put mode , t he t 1io1 a nd t 1io0 bi ts de termine how t he tm out put pin change s sta te when a compare ma tch occurs from the com parator a. the tm output pi n can be setup to switch hi gh, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1oc bit in the tm1c1 register . note that the output level requested by the t1io1 and t1io0 bits must be dif ferent from the initial value setup using the t1oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state, it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odifed by c hanging t hese t wo bi ts. it i s ne cessary t o c hange t he va lues of the t1io1 and t1io0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running bit 3 t1oc : tp1_0, tp1_1, tp1_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1pol : tp1_0, tp1_1, tp1_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0, tp1_1 or tp1_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t1dpx : tm1 pwm period/duty control 0: ccrp C period; ccra C duty 1: ccrp C duty; ccra C period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he standard tm contains two comparators, comparator a and comparator p , either of which can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemen ted if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm mode, single pulse or input capture mode.
rev. 1.00 90 ???? ??? ? 01 ? rev. 1.00 91 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D standard type tm operation modes the st andard t ype t m ca n operat e i n one of five operat ing m odes, com pare ma tch out put mode, pwm mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t naf a nd t npf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr i s h igh n o t npf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf interrupt request fag is ge nerated a fter a c ompare m atch oc curs fro m co mparator a. t he t npf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he tnio1 and tnio0 bits in the tmnc1 register . the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 90 ???? ??? ?01? rev. 1.00 91 ???? ??? ? 01 ? co?nter va??e 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin time ccrp=0 ccrp > 0 co?nter overf?ow ccrp > 0 co?nter c?eared b? ccrp va??e pa?se res?me stop co?nter restart tncclr = 0; tnm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnoc=0 o?tp?t togg?e with tnaf f?ag note tnio [1:0] = 10 active high o?tp?t se?ect here tnio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol is high compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.00 9 ? ???? ??? ? 01 ? rev. 1.00 93 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e 0x3ff ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin time ccra=0 ccra = 0 co?nter overf?ow ccra > 0 co?nter c?eared b? ccra va??e pa?se res?me stop co?nter restart tncclr = 1; tnm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnoc=0 o?tp?t togg?e with tnaf f?ag note tnio [1:0] = 10 active high o?tp?t se?ect here tnio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol is high tnpf not generated no tnaf f?ag generated on ccra overf?ow o?tp?t does not change compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 9? ???? ??? ?01? rev. 1.00 93 ???? ??? ? 01 ? timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t ncclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 5 ? 384 51 ? ? 40 7 ? 8 89 ? 10 ? 4 d ? t ? ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b and ccra = 128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra d ? t ? 1 ? 8 ? 5 ? 384 51 ? ? 40 7 ? 8 89 ? 10 ? 4 the pwm output period cycle is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.00 94 ???? ??? ? 01 ? rev. 1.00 95 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin (tnoc=1) time co?nter c?eared b? ccrp pa?se res?me co?nter stop if tnon bit ?ow co?nter reset when tnon ret?rns high tndpx = 0; tnm [1:0] = 10 pwm d?t? c?c?e set b? ccra pwm res?mes operation o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set b? ccrp tm o/p pin (tnoc=0) pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 94 ???? ??? ?01? rev. 1.00 95 ???? ??? ? 01 ? co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin (tnoc=1) time co?nter c?eared b? ccra pa?se res?me co?nter stop if tnon bit ?ow co?nter reset when tnon ret?rns high tndpx = 1; tnm [1:0] = 10 pwm d?t? c?c?e set b? ccrp pwm res?mes operation o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnpol = 1 pwm period set b? ccra tm o/p pin (tnoc=0) pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation
rev. 1.00 9 ? ???? ??? ? 01 ? rev. 1.00 97 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D single pulse mode to se lect t his mode , bit s tnm1 and t nm0 i n t he t mnc1 regi ster shoul d be se t t o 10 respe ctively and also the tnio1 and tnio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.

? ? ? ? ? ?? ? ? ?? single pulse generation
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 9? ???? ??? ?01? rev. 1.00 97 ???? ??? ? 01 ? co?nter va??e ccrp ccra tnon tnpau tnpol ccrp int. f?ag tnpf ccra int. f?ag tnaf tm o/p pin (tnoc=1) time co?nter stopped b? ccra pa?se res?me co?nter stops b? software co?nter reset when tnon ret?rns high tnm [1:0] = 10 ; tnio [1:0] = 11 p??se width set b? ccra o?tp?t inverts when tnpol = 1 no ccrp interr?pts generated tm o/p pin (tnoc=0) tckn pin software trigger c?eared b? ccra match tckn pin trigger a?to. set b? tckn pin software trigger software c?ear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high. 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode.
rev. 1.00 98 ???? ??? ? 01 ? rev. 1.00 99 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D capture input mode to s elect this mode bits tnm1 and tnm0 in the tm nc1 regis ter s hould be s et to 01 respectively . this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. the external signal is supplied on the tpn_0, tpn_1 or tpn_2 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register . the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0, tpn_1 or tpn_2 pin, the present value in the c ounter wi ll be l atched i nto t he ccra regi sters a nd a t m i nterrupt ge nerated. irrespec tive of what events occur on the tpn_0, tpn_1 or tpn_2 pin the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs, the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse wi dths. the tnio1 and tnio0 bit s ca n se lect the ac tive tri gger edge on the tpn_0, tpn_1 or tpn_2 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0, tpn_1 or tpn_2 pin, however it must be noted that the counter will continue to run. as the tpn_0, tpn_1 or tpn_2 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 98 ???? ??? ?01? rev. 1.00 99 ???? ??? ? 01 ? co?nter va??e yy ccrp tnon tnpau ccrp int. f?ag tnpf ccra int. f?ag tnaf ccra va??e time co?nter c?eared b? ccrp pa?se res?me co?nter reset tnm [1:0] = 01 tm capt?re pin tpn_x xx co?nter stop tnio [1:0] va??e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C fa??ing edge 10 C both edges 11 C disab?e capt?re capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 100 ???? ??? ? 01 ? rev. 1.00 101 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D enhanced type tm C etm the enhanced t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. etm name tm no. tm input pin tm output pin ht ?? f ? 4d ht ?? f ? 5d 10-bit etm 1 tck1 tp1a_0 ? tp1a_1 tp1b_0 ? tp1b_1 ? tp1b_ ? enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock s ource. there are three internal comparators w ith the names, comparator a , comparator b and comparator p . these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3 bits wide whose value is compared with the highest 3 bits in the counter while ccra and ccrb are 10 bits wide and therefore compared with all counter bits. the onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers.
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? ? ? ? enhanced type tm block diagram
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 100 ???? ??? ?01? rev. 1.00 101 ???? ??? ? 01 ? enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. etm register list C HT66F25D only register name bit 7 6 5 4 3 2 1 0 tm1c0 t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr tm1c ? t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d ? d5 d4 d3 d ? d1 d0 tm1dh d9 d8 tm1al d7 d ? d5 d4 d3 d ? d1 d0 tm1ah d9 d8 tm1bl d7 d ? d5 d4 d3 d ? d1 d0 tm1bh d9 d8 10-bit enhanced tm register list tm1dl register register name bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7 ~ bit 0 tm1 10-bit counter bit 7 ~ bit 0 tm1dh register register name bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1dh : tm1 counter high byte register bit 1 ~ bit 0 tm1 10-bit counter bit 9 ~ bit 8 tm1al register register name bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7 ~ bit 0 tm1 10-bit ccra bit 7 ~ bit 0
rev. 1.00 10 ? ???? ??? ? 01 ? rev. 1.00 103 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tm1ah register register name bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1ah : tm1 ccra high byte register bit 1 ~ bit 0 tm1 10-bit ccra bit 9 ~ bit 8 tm1bl register register name bit 7 6 5 4 3 2 1 0 name d7 d ? d5 d4 d3 d ? d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1bl : tm1 ccrb low byte register bit 7 ~ bit 0 tm1 10-bit ccrb bit 7 ~ bit 0 tm1bh register register name bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 bit 1~0 tm1bh : tm1 ccrb high byte register bit 1 ~ bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 tm1c0 register register name bit 7 6 5 4 3 2 1 0 name t1pau t1ck ? t1ck1 t1ck0 t1on t1rp ? t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 10? ???? ??? ?01? rev. 1.00 103 ???? ??? ? 01 ? bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned, can not be selected. 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. the external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f sys is the system clock, while f h and f tbc are other internal clocks, the detai ls of which can be found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm. setting the bit high enables the counter to run while clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn of f the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode, then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compare with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.00 104 ???? ??? ? 01 ? rev. 1.00 105 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tm1c1 register register name bit 7 6 5 4 3 2 1 0 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0 : select tm1 ccra operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm shoul d be switched of f before any changes are made to the t1am1 and t1am0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a_0, tp1a_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1a_0, tp1a_1 01: input capture at falling edge of tp1a_0, tp1a_1 01: input capture at falling/rising edge of tp1a_0, tp1a_1 11: input capture disabled timer/counter mode unused. these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register . note that the output level requested by the t1aio1 and t1aio0 bits must be dif ferent from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state , it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 104 ???? ??? ?01? rev. 1.00 105 ???? ??? ? 01 ? bit 3 t1aoc : tp1a_0, tp1a_1output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a_0, tp1a_1output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a_0 or tp1a_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter . remember that the e nhanced t m c ontains t hree c omparators, com parator a, com parator b a nd comparator p , but only comparator a or comparator p can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implement ed if the ccrp bits are all cleared to zero. the t1cclr bit is not us ed in the s ingle p ulse or input capture mode.
rev. 1.00 10 ? ???? ??? ? 01 ? rev. 1.00 107 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D tm1c2 register register name bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operation mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the t m sh ould b e swi tched o ff b efore a ny c hanges a re m ade t o t he t 1bm1 a nd t1bm0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused. these tw o bits are us ed to determine how the tm output pin changes s tate w hen a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register . note that the output level re quested by t he t 1bio1 a nd t 1bio0 bi ts m ust be di fferent from t he i nitial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state , it can be reset to its initial level by changing the level of the t1on bit from low to high. in t he pwm mode , t he t 1bio1 a nd t 1bio0 bi ts de termine how t he t m out put pi n changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1bio1 and t1bio0 bits only after the tm has been switched of f. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 10? ???? ??? ?01? rev. 1.00 107 ???? ??? ? 01 ? bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no ef fect if the tm is in the t imer/counter mode. in the co mpare ma tch out put mode i t de termines t he l ogic l evel of t he t m ou tput pi n before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tp1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the t imer/counter mode. bit 1~0 t1pwm1 ~t1pwm0: select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down
rev. 1.00 108 ???? ??? ? 01 ? rev. 1.00 109 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D enhanced type tm operation modes the enhanced t ype tm can operat e in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/ counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode ccrb compare match o ? tp ? t mode ccrb timer/co ? nter mode ccrb pwm o ? tp ? t mode ccrb sing ? e p ?? se o ? tp ? t mode ccrb inp ? t capt ? re mode ?: permitted. : not permitted compare match output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all clear ed to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p . when the tncclr bit is low , there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p , the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a tnaf or tnbf interrupt request fag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request flag, generated from a compare match from comparator p , will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the t naio1, t naio0 b its ( for t he t pna_0 o r t pna_1 p in) a nd t nbio1, t nbio0 b its ( for t he tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initia l conditi on of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna_0, tpna_1 or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 108 ???? ??? ?01? rev. 1.00 109 ???? ??? ? 01 ? co?nter va??e 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. f?ag tnpf ccra int. f?ag tnaf tpna o/p pin time ccrp=0 ccrp > 0 co?nter overf?ow ccrp > 0 co?nter c?eared b? ccrp va??e pa?se res?me stop co?nter restart tncclr = 0; tnam [1:0] = 00 o?tp?t pin set to initia? leve? low if tnaoc=0 o?tp?t togg?e with tnaf f?ag note tnaio [1:0] = 10 active high o?tp?t se?ect here tnaio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnapol is high etm ccra compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
rev. 1.00 110 ???? ??? ? 01 ? rev. 1.00 111 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e 0x3ff ccrp ccrb tnon tnpau tnbpol ccrp int. f?ag tnpf ccrb int. f?ag tnbf tpnb o/p pin time ccrp=0 ccrp > 0 co?nter overf?ow ccrp > 0 co?nter c?eared b? ccrp va??e pa?se res?me stop co?nter restart tncclr = 0; tnbm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnboc=0 o?tp?t togg?e with tnbf f?ag note tnbio [1:0] = 10 active high o?tp?t se?ect here tnbio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnbf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnbpol is high etm ccrb compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 110 ???? ??? ?01? rev. 1.00 111 ???? ??? ? 01 ? co?nter va??e 0x3ff ccrp ccra tnon tnpau tnapol ccrp int. f?ag tnpf ccra int. f?ag tnaf tpna o/p pin time ccra=0 ccra = 0 co?nter overf?ow ccra > 0 co?nter c?eared b? ccra va??e pa?se res?me stop co?nter restart tncclr = 1; tnam [1:0] = 00 o?tp?t pin set to initia? leve? low if tnaoc=0 o?tp?t togg?e with tnaf f?ag note tnaio [1:0] = 10 active high o?tp?t se?ect here tnaio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnaf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnapol is high tnpf not generated no tnaf f?ag generated on ccra overf?ow o?tp?t does not change etm ccra compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
rev. 1.00 11 ? ???? ??? ? 01 ? rev. 1.00 113 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e 0x3ff ccrb ccra tnon tnpau tnbpol ccrb int. f?ag tnbf ccra int. f?ag tnaf tpnb o/p pin time ccra=0 ccra = 0 co?nter overf?ow ccra > 0 co?nter c?eared b? ccra va??e pa?se res?me stop co?nter restart tncclr = 1; tnbm [1:0] = 00 o?tp?t pin set to initia? leve? low if tnboc=0 o?tp?t togg?e with tnbf f?ag note tnbio [1:0] = 10 active high o?tp?t se?ect here tnbio [1:0] = 11 togg?e o?tp?t se?ect o?tp?t not affected b? tnbf f?ag. remains high ?nti? reset b? tnon bit o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnbpol is high no tnaf f?ag generated on ccra overf?ow etm ccrb compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 11 ? ???? ??? ?01? rev. 1.00 113 ???? ??? ? 01 ? timer/counter mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 register should all be set high. the t imer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 10 respectively. the p wm function w ithin the tm is us eful for applications w hich require functions such as motor control, heating control, illumination control etc. by providing a signal of fixed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extre mely fexible. in the pwm mode, the tncclr bit is used to determine in which way the pwm period is controlled. w ith the tncclr bit set high, the pwm period can be fnely controlled using the ccra register s. in this case the ccrb registers are used to set the pwm duty value (for tpnb output pins). the ccrp bits are not used and tpna output pins are not used. the pwm output can only be generated on the tpnb output pins. w ith the tncclr bit cleared to zero, the pwm pe riod is set usi ng one of the eight va lues of the three ccrp bi ts, in multiples of 128. now b oth c cra a nd c crb r egisters c an b e u sed t o se tup d ifferent d uty c ycle v alues t o p rovide dual pwm outputs on their relative tpna and tpnb pins. the tnpwm1 and tnpwm0 bits determine the pwm alignment type, which can be either edge or centre type. in edge alignment, the leading edge of the pwm signals will all be generated concurrently when the counter is reset to zero. w ith all power currents switching on at the same time, this may give rise to problems in higher power applications. in centre alignment the centre of the pwm active signals will occur sequentially , thus reducing the level of simultaneous power switching currents. interrupt fags, one for each of the ccra, ccrb and ccrp , will be generated when a compare match occurs from ei ther the com parator a, com parator b or com parator p . the tnaoc and tnboc bits in the tmnc1 and tmnc2 register are used to select the required polarity of the pwm waveform while the two tnaio1, tnaio0 and tnbio1, tnbio0 bits pairs are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnapol and tnbpol bit are used to reverse the polarity of the pwm output waveform.
rev. 1.00 114 ???? ??? ? 01 ? rev. 1.00 115 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D etm, pwm mode, edge-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 1 ? 8 ? 5 ? 384 51 ? ? 40 7 ? 8 89 ? 10 ? 4 a d ? t ? ccra b d ? t ? ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 1 ? 3 511 51 ? 10 ? 1 10 ?? 10 ? 3 b d ? t ? ccrb etm, pwm mode, center-aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ? 5 ? 51 ? 7 ? 8 10 ? 4 1 ? 80 153 ? 179 ? ? 04 ? a d ? t ? (ccra ? ) - 1 b d ? t ? (ccrb ? ) - 1 etm, pwm mode, center-aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period ? 4 ? 10 ?? 10 ? 4 ? 04 ? ? 044 ? 04 ? b d ? t ? (ccrb ? ) - 1
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 114 ???? ??? ?01? rev. 1.00 115 ???? ??? ? 01 ? co?nter va??e ccrp ccra tnon tnpau tnapol ccra int. f?ag tnaf ccrb int. f?ag tnbf tpna pin (tnaoc=1) time co?nter c?eared b? ccrp pa?se res?me stop co?nter restart tncclr = 0; tnam [1:0] = 10? tnbm [1:0] = 10; tnpwm [1:0] = 00 o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnapol is high ccrb ccrp int. f?ag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) d?t? c?c?e set b? ccra d?t? c?c?e set b? ccrb pwm period set b? ccrp d?t? c?c?e set b? ccra d?t? c?c?e set b? ccra etm pwm mode C edge aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty
rev. 1.00 11 ? ???? ??? ? 01 ? rev. 1.00 117 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e ccra tnon tnpau tnbpol ccrb int. f?ag tnbf time co?nter c?eared b? ccra pa?se res?me stop co?nter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 00 o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnbpol is high ccrb ccrp int. f?ag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) d?t? c?c?e set b? ccrb pwm period set b? ccra etm pwm mode C edge aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 11 ? ???? ??? ?01? rev. 1.00 117 ???? ??? ? 01 ? co?nter va??e ccrp ccra tnon tnpau tnapol ccra int. f?ag tnaf ccrb int. f?ag tnbf tpna pin (tnaoc=1) time pa?se res?me stop co?nter restart tncclr = 0; tnam [1:0] = 10? tnbm [1:0] = 10; tnpwm [1:0] = 11 o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction o?tp?t inverts when tnapol is high ccrb ccrp int. f?ag tnpf tpnb pin (tnboc=1) tpnb pin (tnboc=0) d?t? c?c?e set b? ccra d?t? c?c?e set b? ccrb pwm period set b? ccrp etm pwm mode C centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
rev. 1.00 118 ???? ??? ? 01 ? rev. 1.00 119 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e ccra tnon tnpau tnbpol ccra int. f?ag tnaf ccrb int. f?ag tnbf time pa?se res?me stop co?nter restart tncclr = 1; tnbm [1:0] = 10; tnpwm [1:0] = 11 o?tp?t pin reset to initia? va??e o?tp?t contro??ed b? other pin-shared f?nction ccrb tpnb pin (tnboc=1) tpnb pin (tnboc=0) d?t? c?c?e set b? ccrb pwm period set b? ccra o?tp?t inverts when tnbpol is high ccrp int. f?ag tnpf etm pwm mode C centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 118 ???? ??? ?01? rev. 1.00 119 ???? ??? ? 01 ? single pulse output mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge i s a c ompare m atch fr om c omparator b , wh ich c an b e i mplemented u sing t he a pplication program. howe ver i n t he si ngle pul se mod e, t he t non b it c an a lso be m ade t o a utomatically change from low to high using the external tckn pi n, whi ch will in turn initi ate the singl e pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be u sed t o c ontrol t he p ulse wi dth o f t pna. t he c cra-ccrb v alue c an b e u sed t o c ontrol t he pulse widt h of t pnb. a c ompare m atch from com parator a a nd com parator b wil l a lso ge nerate tm inter rupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. tnon bit 0 1 s/w command settnon or tckn pin transition ccrb leading edge tnon bit 1 0 ccra trai?ing edge s/w command clrtnon or ccra compare match tpna o?tp?t pin tpnb o?tp?t pin p??se width = (ccra-ccrb) va??e p??se width = ccra va??e co?nter va??e ccrb ccra 0 time tnon = 1 ccrb compare match tnon bit 1 0 s/w command clrtnon or ccra compare match ccrb trai?ing edge ccra leading edge single pulse generation
rev. 1.00 1 ? 0 ???? ??? ? 01 ? rev. 1.00 1?1 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e ccrb ccra tnon tnpau tnapol ccrb int. f?ag tnbf ccra int. f?ag tnaf tpna pin (tnaoc=1) time co?nter stopped b? ccra pa?se res?me co?nter stops b? software co?nter reset when tnon ret?rns high tnam [1:0] = 10? tnbm [1:0] = 10; tnaio [1:0] = 11? tnbio [1:0] = 11 p??se width set b? (ccra-ccrb) o?tp?t inverts when tnbpol=1 tckn pin software trigger c?eared b? ccra match tckn pin trigger a?to. set b? tckn pin software trigger software c?ear software trigger software trigger tnbpol tpna pin (tnaoc=0) tpnb pin (tnboc=1) tpnb pin (tnboc=0) p??se width set b? ccra o?tp?t inverts when tnapol=1 single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set by the tnon bit high. 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 1 1 and can not be changed.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?0 ???? ??? ?01? rev. 1.00 1 ? 1 ???? ??? ? 01 ? capture input mode to select this mode bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively . this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. t he e xternal si gnal i s su pplied o n t he t pna_0, t pna_1 a nd t pnb_0, t pnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tm nc1 and tm nc2 regis ters. the counter is started when the tno n bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna_0, tpna_1 and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna_0, tpna_1 and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p , a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, t naio0 a nd t nbio1, t nbio0 bi ts c an se lect t he a ctive t rigger e dge on t he t pna_0, tpna_1 and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna_0, tpna_1 and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna_0, tpna_1 and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are not used in this mode.
rev. 1.00 1 ?? ???? ??? ? 01 ? rev. 1.00 1?3 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D co?nter va??e yy ccrp tnon tnpau ccrp int. f?ag tnpf ccra int. f?ag tnaf ccra va??e time co?nter c?eared b? ccrp pa?se res?me co?nter reset tnam [1:0] = 01 tm capt?re pin tpna xx co?nter stop tnaio [1:0] va??e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C fa??ing edge 10 C both edges 11 C disab?e capt?re etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?? ???? ??? ?01? rev. 1.00 1 ? 3 ???? ??? ? 01 ? co?nter va??e yy ccrp tnon tnpau ccrp int. f?ag tnpf ccrb int. f?ag tnbf ccrb va??e time co?nter c?eared b? ccrp pa?se res?me co?nter reset tnbm [1:0] = 01 tm capt?re pin tpnb_x xx co?nter stop tnbio [1:0] va??e xx yy xx yy active edge active edge active edge 00 C rising edge 01 C fa??ing edge 10 C both edges 11 C disab?e capt?re etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function C tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero.
rev. 1.00 1 ? 4 ???? ??? ? 01 ? rev. 1.00 1?5 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.

? ? ? ?? ?? ? ?- -? ? ?? ?? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? -? ? ? ?? ? ? ? ? ?? ? ??
? a/d converter structure a/d converter register description overall operation of the a /d converter is controlled us ing f ve regis ters. a read only regis ter pair exists to store the adc data 12-bit value. the remaining three register s are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl (adrfs=0) d3 d ? d1 d0 adrl (adrfs=1) d7 d ? d5 d4 d3 d ? d1 d0 adrh (adrfs=0) d11 d10 d9 d8 d7 d ? d5 d4 adrh (adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs ? acs1 acs0 adcr1 acs4 vbgen vrefs adck ? adck1 adck0 acerl ace7 ace ? ace5 ace4 ace3 ace ? ace1 ace0 ht66f24d/HT66F25D a/d converter register list
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?4 ???? ??? ?01? rev. 1.00 1 ? 5 ???? ??? ? 01 ? a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow byt e re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d3 d ? d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d ? d5 d4 d3 d ? d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 a nd acerl a re provide d. t hese 8-bi t re gisters de fne func tions such a s t he sel ection of which analog channel is connected to the internal a /d converter , the digitis ed data format, the a / d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs1~acs0 or acs2~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register defne the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 4 analog inputs must be routed to the converter . it is the function of the acs4 and acs1~acs0 or acs2~acs0 bits to determine which analog channel input pins or internal reference voltage, v bg , is actually connected to the internal a/d converter. the acerl control register contains the acer3~acer0 or acer7~acer0 bits which determine which pins on i/o ports are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, cle aring the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin-shared function will be removed. in additio n, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input.
rev. 1.00 1 ?? ???? ??? ? 01 ? rev. 1.00 1?7 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D adcr0 register ? ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs ? acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a.d conversion 010 : start 01 : reset the a/d converter and set eocb to 1 this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running, the bit will be high. bit 5 adoff : a/d module on/off control bit 0: a/d module power on 1: a/d module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : a/d data format control bit 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as 0 bit 2~0 acs2~acs0 : select a/d channel (when acs4 is 0) 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?? ???? ??? ?01? rev. 1.00 1 ? 7 ???? ??? ? 01 ? adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 vbgen vrefs adck ? adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : select internal band gap reference voltage as adc input control 0: disable 1: enable this bit enables the internal band gap reference voltage to be connected to the a/ d converter . the vbgen bit must frst have been set to enable the band gap circuit reference voltage to be used by the a/d converter . when the acs4 bit is set high, the band gap reference voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 vbgen : internal band gap reference voltage control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when t he b it i s se t h igh, t he b and g ap v oltage c an b e u sed b y t he a/ d c onverter. i f the band gap reference voltage is not used by the a/d converter and the l vr/lvd function is disabled then the band gap reference circuit will be automat ically switched off to conserve power . when the band gap reference voltage is switched on for use by the a/ d c onverter, a t ime t bg sh ould b e a llowed f or t he b and g ap c ircuit t o st abilise before implementing an a/d conversion. bit 5 unimplemented, read as 0 bit 4 vrefs : select adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter . if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as 0 bit 2~0 adck2~adck0 : select adc converter clock source 000: f 001: f /2 010: f /4 011: f /8 100: f /16 101: f /32 110: f /64 111: undefned, can not be used. these three bits are used to select the clock source for the a/d converter.
rev. 1.00 1 ? 8 ???? ??? ? 01 ? rev. 1.00 1?9 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D acerl re gister ? ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name ace7 ace ? ace5 ace4 ace3 ace ? ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne i/o pin is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne i/o pin is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne i/o pin is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne i/o pin is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 a/d operation the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o di gital conve rsion process is comple te. this bit will be automatically set to 0 by the micro controller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register , and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program flow to the associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f , can be chosen to be either f or a subdivided version of f . the division ratio value is determined by the
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?8 ???? ??? ?01? rev. 1.00 1 ? 9 ???? ??? ? 01 ? adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the a/d clock source speed range that can be selected. as the recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for selected system clock frequencies. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to 000b or 1 10b. doing so will give a/d clock p eriods t hat a re l ess t han t he m inimum a/ d c lock p eriod o r g reater t han t he m aximum a/ d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2~ adck0 = 000 (f sys ) adck2~ adck0 = 001(f sys /2) adck2~ adck0 = 010(f sys /4) adck2~ adck0 = 011(f sys /8) adck2~ adck0 = 100(f sys /16) adck2~ adck0 = 101(f sys /32) adck2~ adck0 = 110(f sys /64) adck2~ adck0 = 111 1mhz 1s ? s 4s 8s 1 ? s* 3 ? s* ? 4s* undefned ? mhz 500ns 1s ? s 4s 8s 1 ? s* 3 ? s* undefned 4mhz ? 50ns* 500ns 1s ? s 4s 8s 1 ? s* undefned 8mhz 1 ? 5ns* ? 50ns* 500ns 1s ? s 4s 8s undefned 1 ? mhz 83ns* 1 ? 7ns* 333ns* ?? 7ns 1.33s ? . ? 7s 5.33s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bi t i n t he adcr0 re gister. t his bi t m ust be z ero t o powe r on t he a/ d c onverter. w hen the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as i ndicated i n t he t iming di agram, m ust be a llowed be fore a n a/ d c onversion i s i nitiated. e ven if no pins are selected for use as a/d inputs by clearing the ace3~ace0 or ace7~ace0 bits in the acerl register , if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref . the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and other pin functions will be disabled automatically. a/d input pins all of the a /d analog input pins are pin-shared w ith the i/o pins as w ell as other functions . the ace3~ace0 or ace7~ace0 bits in the acerl register determines whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace3~ace0 or ace7~ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/ d converter input and the original pin functions disabled. in this way , pins can be changed under program c ontrol t o c hange t heir f unction b etween a/ d i nputs a nd o ther f unctions. al l p ull-high resistors, w hich are s etup through regis ter programming, w ill be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac port control register to enable the a/d input as when the ace3~ace0 or ace7~ace0 bits enable an a/d input, the status of the port control register will be overridden.
rev. 1.00 130 ???? ??? ? 01 ? rev. 1.00 131 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D the a/d converter has its own reference voltage pin vref however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref .
? ? ? ?? ? ? ? a/d input structure summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4 a nd acs1~acs0 or acs2~acs0 bi ts whi ch a re a lso c ontained i n t he adcr1 a nd adcr0 registers. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace3~ace0 or ace7~ace0 bits in the acerl register. ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set to high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 re gister fr om l ow t o hi gh a nd t hen t o l ow a gain. not e t hat t his bi t sho uld ha ve b een originally cleared to 0. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when t his bit goes l ow. when thi s occurs, the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr register is used, the interrupt enable step above can be omitted.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 130 ???? ??? ?01? rev. 1.00 131 ???? ??? ? 01 ? the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period.

? ? ??? ? ? ???? - ? ? ? ? ? ? ? ? ?
? ? ? ? ? ? ? ? ?? ? a/d conversion timing programming considerations during microcontroller operates where the a/d converter is not being used, the a/d internal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the vdd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb = (v or v ref the a/d converter input voltage value can be calculated using the following equation: a /d input voltage = a/d output digital value (v or v ref the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd level.
rev. 1.00 13 ? ???? ??? ? 01 ? rev. 1.00 133 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D

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? ideal a/d transfer function a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example 1: using an eocb polling method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off the band gap reference voltage clr a doff mov a ,0fh ; setup acerl register to confgure pins an0~an3 mov ac erl,a mov a,00h mov a dcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d polling_eoc: sz e ocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp p olling_eoc ; continue polling mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : jmp st art_conversion ; start next a/d conversion
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 13? ???? ??? ?01? rev. 1.00 133 ???? ??? ? 01 ? example 2: using the interrupt method to detect the end of conversion clr a de ; disable adc interrupt mov a,03h mov a dcr1,a ; select f sys /8 as a/d clock and switch off the band gap reference voltage clr a doff mov a ,0fh ; setup acerl register to confgure pins an0~an3 mov ac erl,a mov a,00h mov a dcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr st art ; high pulse on start bit to initiate conversion set s tart ; reset a/d clr s tart ; start a/d clr a df ; clear adc interrupt request fag set a de ; enable adc interrupt set e mi ; enable global interrupt : ; adc interrupt service routine adc_isr: mov ac c_stack,a ; save acc to user defned memory mov a ,status mov s tatus_stack,a ; save status to user defned memory : mov a ,adrl ; read low byte conversion result value mov a drl_buffer,a ; save result to user defned register mov a ,adrh ; read high byte conversion result value mov a drh_buffer,a ; save result to user defned register : exit_int_isr: mov a ,status_stack mov s tatus,a ; restore status from user defned memory mov a ,acc_stack ; restore acc from user defned memory reti
rev. 1.00 134 ???? ??? ? 01 ? rev. 1.00 135 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0 and int1 pins while the internal interrupts are generated by various internal functions such as the tms, t ime base, lvd and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0 or mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/ disable bit or f for request fag. function enable bit request flag notes g ? oba ? emi intn pins intne intnf n = 0 or 1 m ?? ti-f ? nction mfne mfnf n = 0 ~ ? a/d converter ade adf time base tbe tbf n = 0 or 1 lvd lve lvf eeprom dee def tm tnpe tnpf n = 0 or 1 tnae tnaf tnbe tnbf n = 1 interrupt register bit naming conventions
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 134 ???? ??? ?01? rev. 1.00 135 ???? ??? ? 01 ? ht66f24d interrupt register list register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f int1f int0f mf0e int1e int0e emi intc1 tb1f tb0f adf mf1f tb1e tb0e ade mf1e intc ? mf ? f mf ? e mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi ? def lvf dee lve HT66F25D interrupt register list register name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 mf0f int1f int0f mf0e int1e int0e emi intc1 tb1f tb0f adf mf1f tb1e tb0e ade mf1e intc ? mf ? f mf ? e mfi0 t0af t0pf t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi ? def lvf dee lve integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 int1s1~int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 01: both rising and falling edges bit 1~0 int0s1~int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 01: both rising and falling edges
rev. 1.00 13 ? ???? ??? ? 01 ? rev. 1.00 137 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D intc0 register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name mf0f int1f int0f mf0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 mf0f : multi-function 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 mf0e : multi-function 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 13? ???? ??? ?01? rev. 1.00 137 ???? ??? ? 01 ? intc1 register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name tb1f tb0f adf mf1f tb1e tb0e ade mf1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tb1f : t ime base 1 interrupt request fag 0: no request 1: interrupt request bit 6 tb0f : t ime base 0 interrupt request fag 0: no request 1: interrupt request bit 5 adf : a/d converter interrupt request fag 0: no request 1: interrupt request bit 4 mf1f : multi-function 1 interrupt request fag 0: no request 1: interrupt request bit 3 tb1e : t ime base 1 interrupt control 0: disable 1: enable bit 2 tb0e : t ime base 0 interrupt control 0: disable 1: enable bit 1 ade : a/d converter interrupt control 0: disable 1: enable bit 0 mf1e : multi-function 1 interrupt control 0: disable 1: enable intc2 register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name mf ? f mf ? e r/w r/w r/w por 0 0 bit 7~5 unimplemented, read as 0 bit 4 mf2f : multi-function 2 interrupt request fag 0: no request 1: interrupt request bit 3~1 unimplemented, read as 0 bit 0 mf2e : multi-function 2 interrupt control 0: disable 1: enable
rev. 1.00 138 ???? ??? ? 01 ? rev. 1.00 139 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D mfi0 register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register - ht66f24d bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 138 ???? ??? ?01? rev. 1.00 139 ???? ??? ? 01 ? mfi1 register - HT66F25D bit 7 6 5 4 3 2 1 0 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 t1bf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as 0 bit 2 t1be : tm1 comparator b match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register - ht66f24d/HT66F25D bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as 0 bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable
rev. 1.00 140 ???? ??? ? 01 ? rev. 1.00 141 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p , comparator a or comparator b match or a/d conversion completion, etc., the relevant interrupt request fag will be set. w hether t he r equest fa g a ctually g enerates a p rogram j ump t o t he r elevant i nterrupt v ector i s determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an act ual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated w ith a reti, w hich retrieves the original p rogram counter addres s from the st ack a nd a llows t he m icrocontroller t o c ontinue wi th n ormal e xecution a t t he p oint wh ere t he interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 140 ???? ??? ?01? rev. 1.00 141 ???? ??? ? 01 ? int0 pin int1 pin int0f int1f int0e int1e emi 04h emi 08h m. f?nct. 0 mf0f mf0e emi 0ch emi 10h a/d adf ade emi 14h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch interr?pt name req?est f?ags enab?e bits master enab?e vector emi a?to disab?ed in isr priorit? high low tm1 p t1pf t1pe tm1 a t1af t1ae m. f?nct. 1 mf1f mf1e tm0 p t0pf t0pe tm0 a t0af t0ae interr?pts contained within m??ti-f?nction interr?pts time base 1 tb1f tb1e emi ?0h m. f?nct. ? mf?f mf?e eeprom def dee xxe enab?e bits xxf req?est f?ag? a?to reset in isr legend xxf req?est f?ag? no a?to reset in isr interrupt scheme C ht66f24d int0 pin int1 pin int0f int1f int0e int1e emi 04h emi 08h m. f?nct. 0 mf0f mf0e emi 0ch emi 10h a/d adf ade emi 14h time base 0 tb0f tb0e emi 18h lvd lvf lve emi 1ch interr?pt name req?est f?ags enab?e bits master enab?e vector emi a?to disab?ed in isr priorit? high low tm1 p t1pf t1pe tm1 a t1af t1ae m. f?nct. 1 mf1f mf1e tm0 p t0pf t0pe tm0 a t0af t0ae interr?pts contained within m??ti-f?nction interr?pts tm1 b t1bf t1be eeprom def dee time base 1 tb1f tb1e emi ?0h m. f?nct. ? mf?f mf?e xxe enab?e bits xxf req?est f?ag? a?to reset in isr legend xxf req?est f?ag? no a?to reset in isr interrupt scheme C HT66F25D
rev. 1.00 14 ? ???? ??? ? 01 ? rev. 1.00 143 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D external interrupt the external interrupts are controlled by signal transitions on the pins int0~int1. an external interrupt request will take place when the external interrupt request fags, int0f~int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int1e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the externa l interrupt functio n and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register . when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. multi-function interrupt within thes e devices there are up to s even m ulti-function interrupts . u nlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm, lvd or data eeprom interrupts. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm , l vd or d ata eepro m interrupts , w ill not be automatically res et and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 14? ???? ??? ?01? rev. 1.00 143 ???? ??? ? 01 ? time base interrupt the function of the t ime base interrupt is to provide regular time signal in the form of an internal interrupt. it is controlled by the overflow s ignal from the res pective timer function. when this happens, the respective interrupt request fags, tb0f or tb1f , will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit emi and the corres ponding t ime base enable bit, tb0e or tb1e, must f rst be s et. when the interrupt is enabled, the stack is not full and the t ime base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock so urces o riginate f rom t he i nternal c lock so urce f tb. t his f tb i nput c lock p asses t hrough a di vider, t he di vision ra tio of whi ch i s se lected by progra mming t he a ppropriate bi ts i n t he t bc register to obtain longer interrupt periods whose value ranges. the clock source that generates ftb, which in turn controls the t ime base interrupt period, can originate from several dif ferent sources, as shown in the system operating mode section. tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb0 ? tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : t ime base control 0: disable 1: enable bit 6 tbck : t ime base clock f tb selection 0: f 1: f /4 bit 5~4 tb11~tb10 : select t ime base 1 t ime-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb
rev. 1.00 144 ???? ??? ? 01 ? rev. 1.00 145 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D f sys /4 f tbc m u x tbck f tb ? 8 ~ ? 15 tb0?~tb00 time base 0 interr?pt ? 1? ~ ? 15 tb11~tb10 time base 1 interr?pt m u x config?ration option lxt lirc lvd interrupt the low v oltage detector interrupt is contained within the multi-function interrupt. a l vd interrupt reques t w ill take place w hen the l vd interrupt reques t flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low v oltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the multi-function interrupt vector , will take place. when the low v oltage interrupt is serviced, the emi bit wi ll be aut omatically cl eared t o disable othe r i nterrupts, howeve r only t he mul ti-function interrupt request fag will be also automatically cleared. as the l vf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupt the compact and standard t ype tms have two interrupts each, while the enhanced t ype tm has three interrupts. all of the tm inter rupts are contained within the multi-function interrupts in these devices. for each of the compact and standard t ype tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced t ype tm there are three interrupt request fags tnpf , tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions o n t he e xternal i nterrupt p ins, a l ow p ower su pply v oltage o r c omparator i nput c hange may cause their respective interrupt fag to be set high and consequent ly generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no ef fect on the interrupt wake-up function.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 144 ???? ??? ?01? rev. 1.00 145 ???? ??? ? 01 ? programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf2f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.00 14 ? ???? ??? ? 01 ? rev. 1.00 147 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D low voltage detector C lvd each device has a low v oltage detector function, also known as l vd. this enabled the device to monitor the power supply voltage, vdd, and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be deter mined. a low voltage condition is indicated when the l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the pres et low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd ? vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as 0 bit 5 lvdo : lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvdon : low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as 0 bit 2~0 vlvd2~vlvd0 : select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 14? ???? ??? ?01? rev. 1.00 147 ???? ??? ? 01 ? lvd operation the low v oltage detector function operates by comparing the power supply voltage, vdd, with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.4v . when t he power suppl y vol tage, vdd, fa lls be low t his pre -determined va lue, t he l vdo bi t wi ll be set high indica ting a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay tl vds should be allowed for the circuit ry to stabilise before reading the lvdo bit. note also that as the vdd voltage may rise and fall rather slowly, at the voltage nears that of vl vd, there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of tl vd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interrupt to be generated if vdd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the l vf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.00 148 ???? ??? ? 01 ? rev. 1.00 149 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardwa re programmi ng tools, onc e they are sel ected they cannot be changed la ter using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed s ? stem osci ?? ator se ? ection - f h : hxt ? hirc ? high speed interna ? rc freq ? enc ? se ? ection - f hirc : 4mhz ? 8mhz or 1 ? mhz 3 low speed s ? stem osci ?? ator se ? ection - f l : lxt ? lirc 4 f sub osci ?? ator se ? ection C f sub : lxt ? lirc watchdog options 5 watchdog timer: a ? wa ? s enab ? ed or contro ?? ed b ? software register
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 148 ???? ??? ?01? rev. 1.00 149 ???? ??? ? 01 ? application circuits

rev. 1.00 150 ???? ??? ? 01 ? rev. 1.00 151 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D instruction set introduction central t o t he su ccessful o peration o f a ny m icrocontroller i s i ts i nstruction se t, wh ich i s a se t o f program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microco ntrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for e asier unde rstanding of t he vari ous i nstruction c odes, t hey have bee n subdi vided i nto se veral functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp , cal l, re t, re ti a nd t able re ad i nstructions, i t i s i mportant t o re alize t hat a ny ot her instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involve s a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator . one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the abili ty to perform certain arithm etic operations and data manipula tion is a necessary feature of most microcontroller applications. w ithin the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition a nd less than 0 for subtraction. t he increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 150 ???? ??? ?01? rev. 1.00 151 ???? ??? ? 01 ? logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.00 15 ? ???? ??? ? 01 ? rev. 1.00 153 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a ? [m] add data memor ? to acc 1 z ? c ? ac ? ov addm a ? [m] add acc to data memor ? 1 note z ? c ? ac ? ov add a ? x add immediate data to acc 1 z ? c ? ac ? ov adc a ? [m] add data memor ? to acc with carr ? 1 z ? c ? ac ? ov adcm a ? [m] add acc to data memor ? with carr ? 1 note z ? c ? ac ? ov sub a ? x s ? btract immediate data from the acc 1 z ? c ? ac ? ov sub a ? [m] s ? btract data memor ? from acc 1 z ? c ? ac ? ov subm a ? [m] s ? btract data memor ? from acc with res ?? t in data memor ? 1 note z ? c ? ac ? ov sbc a ? [m] s ? btract data memor ? from acc with carr ? 1 z ? c ? ac ? ov sbcm a ? [m] s ? btract data memor ? from acc with carr ?? res ?? t in data memor ? 1 note z ? c ? ac ? ov daa [m] decima ? adj ? st acc for addition with res ?? t in data memor ? 1 note c logic operation and a ? [m] logica ? and data memor ? to acc 1 z or a ? [m] logica ? or data memor ? to acc 1 z xor a ? [m] logica ? xor data memor ? to acc 1 z andm a ? [m] logica ? and acc to data memor ? 1 note z orm a ? [m] logica ? or acc to data memor ? 1 note z xorm a ? [m] logica ? xor acc to data memor ? 1 note z and a ? x logica ? and immediate data to acc 1 z or a ? x logica ? or immediate data to acc 1 z xor a ? x logica ? xor immediate data to acc 1 z cpl [m] comp ? ement data memor ? 1 note z cpla [m] comp ? ement data memor ? with res ?? t in acc 1 z increment & decrement inca [m] increment data memor ? with res ?? t in acc 1 z inc [m] increment data memor ? 1 note z deca [m] decrement data memor ? with res ?? t in acc 1 z dec [m] decrement data memor ? 1 note z rotate rra [m] rotate data memor ? right with res ?? t in acc 1 none rr [m] rotate data memor ? right 1 note none rrca [m] rotate data memor ? right thro ? gh carr ? with res ?? t in acc 1 c rrc [m] rotate data memor ? right thro ? gh carr ? 1 note c rla [m] rotate data memor ? ? eft with res ?? t in acc 1 none rl [m] rotate data memor ? ? eft 1 note none rlca [m] rotate data memor ? ? eft thro ? gh carr ? with res ?? t in acc 1 c rlc [m] rotate data memor ? ? eft thro ? gh carr ? 1 note c
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 15? ???? ??? ?01? rev. 1.00 153 ???? ??? ? 01 ? mnemonic description cycles flag affected data move mov a ? [m] move data memor ? to acc 1 none mov [m] ? a move acc to data memor ? 1 note none mov a ? x move immediate data to acc 1 none bit operation clr [m].i c ? ear bit of data memor ? 1 note none set [m].i set bit of data memor ? 1 note none branch ? mp addr ?? mp ? nconditiona ??? ? none sz [m] skip if data memor ? is zero 1 note none sza [m] skip if data memor ? is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memor ? is zero 1 note none snz [m].i skip if bit i of data memor ? is not zero 1 note none siz [m] skip if increment data memor ? is zero 1 note none sdz [m] skip if decrement data memor ? is zero 1 note none siza [m] skip if increment data memor ? is zero with res ?? t in acc 1 note none sdza [m] skip if decrement data memor ? is zero with res ?? t in acc 1 note none call addr s ? bro ? tine ca ?? ? none ret ret ? rn from s ? bro ? tine ? none ret a ? x ret ? rn from s ? bro ? tine and ? oad immediate data to acc ? none reti ret ? rn from interr ? pt ? none table read tabrdc [m] read tab ? e (c ? rrent page) to tblh and data memor ? ? note none tabrdl [m] read tab ? e ( ? ast page) to tblh and data memor ? ? note none miscellaneous nop no operation 1 none clr [m] c ? ear data memor ? 1 note none set [m] set data memor ? 1 note none clr wdt c ? ear watchdog timer 1 to ? pdf clr wdt1 pre-c ? ear watchdog timer 1 to ? pdf clr wdt ? pre-c ? ear watchdog timer 1 to ? pdf swap [m] swap nibb ? es of data memor ? 1 note none swapa [m] swap nibb ? es of data memor ? with res ?? t in acc 1 none halt enter power down mode 1 to ? pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the t o and pdf fags may be af fected by the execution status. the t o and pdf fags are cleared after both "clr wdt1" and "clr wdt2" i nstructions a re c onsecutively e xecuted. ot herwise t he t o a nd pdf fl ags re main unchanged.
rev. 1.00 154 ???? ??? ? 01 ? rev. 1.00 155 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 154 ???? ??? ?01? rev. 1.00 155 ???? ??? ? 01 ? call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z cpla [m] complement d ata m emory wi th r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c
rev. 1.00 15 ? ???? ??? ? 01 ? rev. 1.00 157 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 15? ???? ??? ?01? rev. 1.00 157 ???? ??? ? 01 ? mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none
rev. 1.00 158 ???? ??? ? 01 ? rev. 1.00 159 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 [ m].0 affected f ag(s) none rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 c c [ m].0 affected f ag(s) c
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 158 ???? ??? ?01? rev. 1.00 159 ???? ??? ? 01 ? rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m] = 0 affected f ag(s) none sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc = 0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none
rev. 1.00 1 ? 0 ???? ??? ? 01 ? rev. 1.00 1?1 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m] = 0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc = 0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7 ~ [ m].4 affected f ag(s) none
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?0 ???? ??? ?01? rev. 1.00 1 ? 1 ???? ??? ? 01 ? swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3 ~ a cc.0 [ m].7 ~ [ m].4 acc.7 ~ a cc.4 [ m].3 ~ [ m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] = 0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m] = 0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i = 0 affected f ag(s) none tabrd [m] read ta ble to t blh a nd d ata m emory description the p rogram c ode a ddressed b y t he t able p ointer ( tbhp a nd t blp) is m oved t o t he sp ecifed data m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none
rev. 1.00 1 ?? ???? ??? ? 01 ? rev. 1.00 1?3 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?? ???? ??? ?01? rev. 1.00 1 ? 3 ???? ??? ? 01 ? package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 16-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.780 0.880 b 0. ? 40 0. ? 80 c 0.115 0.195 d 0.115 0.150 e 0.014 0.0 ?? f 0.045 0.070 g 0.100 h 0.300 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a 19.81 ?? .35 b ? .10 7.11 c ? .9 ? 4.95 d ? .9 ? 3.81 e 0.3 ? 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? 8. ?? i 10.9 ?
rev. 1.00 1 ? 4 ???? ??? ? 01 ? rev. 1.00 1?5 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 0.735 D 0.775 b 0. ? 40 D 0. ? 80 c 0.115 D 0.195 d 0.115 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.070 g D 0.100 D h 0.300 D 0.3 ? 5 i D 0.430 D symbol dimensions in mm min. nom. max. a 18. ? 7 D 19. ? 9 b ? .10 D 7.11 c ? .9 ? D 4.95 d ? .9 ? D 3.81 e 0.3 ? D 0.5 ? f 1.14 D 1.78 g D ? .54 D h 7. ?? D 8. ?? i D 10.9 ? D mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.745 D 0.785 b 0. ? 75 D 0. ? 95 c 0.1 ? 0 D 0.150 d 0.110 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.0 ? 0 g D 0.100 D h 0.300 D 0.3 ? 5 i D 0.430 D symbol dimensions in mm min. nom. max. a 18.9 ? D 19.94 b ? .99 D 7.49 c 3.05 D 3.81 d ? .79 D 3.81 e 0.3 ? D 0.5 ? f 1.14 D 1.5 ? g D ? .54 D h 7. ?? D 8. ?? i D 10.9 ? D
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?4 ???? ??? ?01? rev. 1.00 1 ? 5 ???? ??? ? 01 ? 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0. ?? 8 D 0. ? 44 b 0.150 D 0.157 c 0.01 ? D 0.0 ? 0 c' 0.38 ? D 0.40 ? d D D 0.0 ? 9 e D 0.050 D f 0.004 D 0.010 g 0.01 ? D 0.050 h 0.007 D 0.010 0 D 8 symbol dimensions in mm min. nom. max. a 5.79 D ? . ? 0 b 3.81 D 3.99 c 0.30 D 0.51 c' 9.80 D 10. ? 1 d D D 1.75 e D 1. ? 7 D f 0.10 D 0. ? 5 g 0.41 D 1. ? 7 h 0.18 D 0. ? 5 0 D 8
rev. 1.00 1 ?? ???? ??? ? 01 ? rev. 1.00 1?7 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D 20-pin dip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 0.980 D 1.0 ? 0 b 0. ? 40 D 0. ? 80 c 0.115 D 0.195 d 0.115 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.070 g D 0.100 D h 0.300 D 0.3 ? 5 i D 0.430 D symbol dimensions in mm min. nom. max. a ? 4.89 D ?? .9 ? b ? .10 D 7.11 c ? .9 ? D 4.95 d ? .9 ? D 3.81 e 0.3 ? D 0.5 ? f 1.14 D 1.78 g D ? .54 D h 7. ?? D 8. ?? i D 10.9 ? D
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?? ???? ??? ?01? rev. 1.00 1 ? 7 ???? ??? ? 01 ? ms-095a (see fg2) symbol dimensions in inch min. nom. max. a 0.945 D 0.985 b 0. ? 75 D 0. ? 95 c 0.1 ? 0 D 0.150 d 0.110 D 0.150 e 0.014 D 0.0 ?? f 0.045 D 0.0 ? 0 g D 0.100 D h 0.300 D 0.3 ? 5 i D 0.430 D symbol dimensions in mm min. nom. max. a ? 4.00 D ? 5.0 ? b ? .99 D 7.49 c 3.05 D 3.81 d ? .79 D 3.81 e 0.3 ? D 0.5 ? f 1.14 D 1.5 ? g D ? .54 D h 7. ?? D 8. ?? i D 10.9 ? D
rev. 1.00 1 ? 8 ???? ??? ? 01 ? rev. 1.00 1?9 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0. ? 5 ? D 0.300 c 0.01 ? D 0.0 ? 0 c' 0.49 ? D 0.51 ? d D 0.104 e 0.050 D f 0.004 D 0.01 ? g 0.01 ? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10. ? 4 b ? .50 D 7. ?? c 0.30 D 0.51 c' 1 ? . ? 0 D 13.00 d D ? . ? 4 e 1. ? 7 D f 0.10 D 0.30 g 0.41 D 1. ? 7 h 0. ? 0 D 0.33 0 D 8
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 1?8 ???? ??? ?01? rev. 1.00 1 ? 9 ???? ??? ? 01 ? 24-pin skdip (300mil) outline dimensions fig1. full lead packages fig2. 1/2 lead packages ms-001d (see fg1) symbol dimensions in inch min. nom. max. a 1. ? 30 D 1. ? 80 b 0. ? 40 D 0. ? 80 c 0.115 D 0.195 d 0.115 D 0.150 e 0.114 0.0 ?? f 0.045 D 0.070 g 0.100 h 0.300 D 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a 31. ? 4 D 3 ? .51 b ? .10 D 7.11 c ? .9 ? D 4.95 d ? .9 ? D 3.81 e 0.3 ? D 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? D 8. ?? i 10.9 ?
rev. 1.00 170 ???? ??? ? 01 ? rev. 1.00 171 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D ms-001d (see fg2) symbol dimensions in inch min. nom. max. a 1.1 ? 0 D 1.195 b 0. ? 40 D 0. ? 80 c 0.115 D 0.195 d 0.115 D 0.150 e 0.114 0.0 ?? f 0.045 D 0.070 g 0.100 h 0.300 D 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a ? 9.4 ? D 30.35 b ? .10 D 7.11 c ? .9 ? D 4.95 d ? .9 ? D 3.81 e 0.3 ? D 0.5 ? f 1.14 1.78 g ? .54 h 7. ?? D 8. ?? i 10.9 ? mo-095a (see fg2) symbol dimensions in inch min. nom. max. a 1.145 D 1.185 b 0. ? 75 D 0. ? 95 c 0.1 ? 0 D 0.150 d 0.110 D 0.150 e 0.014 0.0 ?? f 0.045 D 0.0 ? 0 g 0.100 h 0.300 D 0.3 ? 5 i 0.430 symbol dimensions in mm min. nom. max. a ? 9.08 D 30.10 b ? .99 D 7.49 c 3.05 D 3.81 d ? .79 D 3.81 e 0.3 ? D 0.5 ? f 1.14 1.5 ? g ? .54 h 7. ?? D 8. ?? i 10.9 ?
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 170 ???? ??? ?01? rev. 1.00 171 ???? ??? ? 01 ? 24-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0. ? 5 ? D 0.300 c 0.01 ? D 0.0 ? 0 c 0.598 D 0. ? 13 d D D 0.104 e D 0.050 D f 0.004 D 0.01 ? g 0.01 ? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10. ? 4 b ? .50 D 7. ?? c 0.30 D 0.51 c 15.19 D 15.57 d D D ? . ? 4 e D 1. ? 7 D f 0.10 D 0.30 g 0.41 D 1. ? 7 h 0. ? 0 D 0.33 0 D 8
rev. 1.00 17 ? ???? ??? ? 01 ? rev. 1.00 173 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D 28-pin skdip (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 1.375 D 1.395 b 0. ? 78 D 0. ? 98 c 0.1 ? 5 D 0.135 d 0.1 ? 5 D 0.145 e 0.01 ? 0.0 ? 0 f 0.050 D 0.070 g 0.100 h ? . ? 95 D 0.315 i 0.375 symbol dimensions in mm min. nom. max. a 34.93 D 35.43 b 7.0 ? D 7.57 c 3.18 D 3.43 d 3.18 D 3. ? 8 e 0.41 D 0.51 f 1. ? 7 D 1.78 g D ? .54 D h 7.49 D 8.00 i D 9.53 D
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 17? ???? ??? ?01? rev. 1.00 173 ???? ??? ? 01 ? 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 D 0.419 b 0. ? 5 ? D 0.300 c 0.01 ? D 0.0 ? 0 c 0. ? 97 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.01 ? g 0.01 ? D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a 9.98 D 10. ? 4 b ? .50 D 7. ?? c 0.30 D 0.51 c 17.70 D 18.11 d D D ? . ? 4 e D 1. ? 7 D f 0.10 D 0.30 g 0.41 D 1. ? 7 h 0. ? 0 D 0.33 0 D 8
rev. 1.00 174 ???? ??? ? 01 ? rev. 1.00 175 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D reel dimensions 16-pin nsop (150mil) symbo description dimensions in mm a ree ? o ? ter diameter 330.01.0 b ree ? inner diameter 100.01.5 c spind ? e ho ? e diameter 13.0 +0.5/-0. ? d ke ? s ? it width ? .00.5 t1 space between f ? ange 1 ? .8 +0.3/-0. ? t ? ree ? thickness ?? . ? 0. ? sop 20w (300mil), sop 24w (300mil), sop 28w (300mil) symbo description dimensions in mm a ree ? o ? ter diameter 330.01.0 b ree ? inner diameter 100.01.5 c spind ? e ho ? e diameter 13.0 +0.5/-0. ? d ke ? s ? it width ? .00.5 t1 space between f ? ange ? 4.8 +0.3/-0. ? t ? ree ? thickness 30. ? 0. ?
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 174 ???? ??? ?01? rev. 1.00 175 ???? ??? ? 01 ? carrier tape dimensions

16-pin nsop (150mil) symbo description dimensions in mm w carrier tape width 1 ? .00.3 p cavit ? pitch 8.00.1 e perforation position 17.50.1 f cavit ? to perforation (width direction) 7.50.1 d perforation diameter 1.55 0.10/-0.00 d1 cavit ? ho ? e diameter 1.50 0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation (length direction) ? .00.1 a0 cavit ? length ? .50.1 b0 cavit ? width 10.30.1 k0 cavit ? depth ? .10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1
rev. 1.00 17 ? ???? ??? ? 01 ? rev. 1.00 177 ???? ??? ?01? a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D sop 20w (300mil) symbo description dimensions in mm w carrier tape width ? 4.0 +0.3/-0.1 p cavit ? pitch 1 ? .00.1 e perforation position 1.750.10 f cavit ? to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation (length direction) ? .00.1 a0 cavit ? length 10.80.1 b0 cavit ? width 13.30.1 k0 cavit ? depth 3. ? 0.1 t carrier tape thickness 0.300.05 c cover tape width ? 1.30.1 sop 24w (300mil) symbol description dimensions in mm w carrier tape width ? 4.0+0.3 p cavit ? pitch 1 ? .00.1 e perforation position 1.750.1 f cavit ? to perforation (width direction) 11.50.1 d perforation diameter 1.55 +0.1/-0.00 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation (length direction) ? .00.1 a0 cavit ? length 10.90.1 b0 cavit ? width 15.90.1 k0 cavit ? depth 3.10.1 t carrier tape thickness 0.350.05 c cover tape width ? 1.30.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width ? 4.0+0.3 p cavit ? pitch 1 ? .00.1 e perforation position 1.750.10 f cavit ? to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavit ? ho ? e diameter 1.50 +0. ? 5/-0.00 p0 perforation pitch 4.00.1 p1 cavit ? to perforation (length direction) ? .00.1 a0 cavit ? length 10.850.10 b0 cavit ? width 18.340.10 k0 cavit ? depth ? .970.10 t carrier tape thickness 0.350.01 c cover tape width ? 1.30.1
a/d flash type 8-bit mcu with eeprom ht66f24d/HT66F25D rev. 1.00 17? ???? ??? ?01? rev. 1.00 177 ???? ??? ? 01 ? holtek semiconductor inc. (headquarters) no.3 ? creation rd. ii ? science park ? hsinch ?? taiwan te ? : 88 ? -3-5 ? 3-1999 fax: 88 ? -3-5 ? 3-1189 http://www.ho ? tek.com.tw holtek semiconductor inc. (taipei sales offce) 4f- ?? no. 3- ?? y ? anq ? st. ? nankang software park ? taipei 115 ? taiwan te ? : 88 ? - ? - ?? 55-7070 fax: 88 ? - ? - ?? 55-7373 fax: 88 ? - ? - ?? 55-7383 (internationa ? sa ? es hot ? ine) holtek semiconductor inc. (shenzhen sales offce) 5f ? unit a ? prod ? ctivit ? b ? i ? ding ? no.5 gaoxin m ? nd road ? nanshan district ? shenzhen ? china 518057 te ? : 8 ? -755-8 ? 1 ? -9908 ? 8 ? -755-8 ? 1 ? -9308 fax: 8 ? -755-8 ? 1 ? -97 ?? holtek semiconductor (usa), inc. (north america sales offce) 4 ? 7 ? 9 fremont b ? vd. ? fremont ? ca 94538 ? usa te ? : 1-510- ? 5 ? -9880 fax: 1-510- ? 5 ? -9885 http://www.ho ? tek.com cop ? right ? ? 01 ? b ? holtek semiconductor inc. the information appearing in this data sheet is be ? ieved to be acc ? rate at the time of p ? b ? ication. however ? ho ? tek ass ? mes no responsibi ? it ? ar ising from the ? se of the specifications described. the app ? ications mentioned herein are ? sed so ? e ?? for the p ? rpose of i ??? stration and ho ? tek makes no warrant ? or representation that s ? ch app ? ications wi ?? be s ? itab ? e witho ? t f ? rther modification ? nor recommends the ? se of its prod ? cts for app ? ication that ma ? present a risk to h ? man ? ife d ? e to ma ? f ? nction or otherwise. ho ? tek's prod ? cts are not a ? thorized for ? se as critica ? components in ? ife support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most ? p-to-date information ? p ? ease visit o ? r web site at http://www.ho ? tek.com.tw.

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